COP8TAB9 Datasheet, PDF (45/59 Pages) National Semiconductor (TI) – 8-Bit CMOS Flash Microcontroller with 2k Byte or 4k Byte Memory

17.0 ACCESS.Bus Interface
(Continued)
GCMEN
ACK
INTEN
STOP
START
The Global Call Match Enable bit enables
the match of an incoming address byte to
the general call address (Start Condition
followed by address byte of 00) while the
ACB is in slave mode.
The Acknowledge bit holds the value this
device sends in master or slave mode during
the next acknowledge cycle. Setting this bit
to 1 instructs the transmitting device to stop
sending data, because the receiver either
does not need, or cannot receive, any more
data.
The Interrupt Enable bit controls generating
ACB interrupts. When the INTEN bit is set,
interrupts are enabled. An interrupt is
generated on any of the following events:
• An address MATCH is detected
(ACBST.NMATCH = 1) and the NMINTE
bit is set.
• A Bus Error occurs (ACBST.BERR = 1).
• Negative acknowledge after sending a
byte (ACBST.NEGACK = 1).
• An interrupt is generated on acknowledge
of each transaction (same as hardware
setting the ACBST.SDAST bit).
• Detection of a Stop Condition while in
slave receive mode (ACBST.SLVSTP =
1).
The Stop bit in master mode generates a
Stop Condition that completes or aborts the
current message transfer.
The Start bit is set to generate a Start
Condition on the ACCESS.Bus. This bit
should be set only when in Master mode or
when requesting Master mode. An address
send sequence should then be performed.
17.9 ACB CONTROL REGISTER 2 (ACBCTL2)
The ACBCTL2 register is a byte-wide, read/write register
that controls the module and selects the ACB clock rate. At
reset, the ACBCTL2 register is cleared.
7
SCLFRQ
1
0
ENABLE
SCLFRQ
The SCL Frequency field specifies the
SCL period (low time and high time) in
master mode. The clock low time and
high time are defined as follows:
t_SCLK1 = t_SCLKh = 2 x SCLFRQ x t_SCLK
Where tCLK is this device’s clock
period when in Active mode. The
SCLFRQ field may be programmed to
values in the range of 0001000
through 1111111.
ENABLE
The Enable bit controls the ACB
module. When this bit is set, the ACB
module is enabled. When the Enable
bit is clear, the ACB module is
disabled, the ACBCTL1, ACBST, and
ACBCST registers are cleared, and the
ACB module clocks are halted.
17.10 ACB OWN ADDRESS REGISTER (ACBADDR)
The ACBADDR register is a byte-wide, read/write register
that holds the module’s first ACCESS.Bus address.
7
6
0
SEAN
ADDR
SAEN
ADDR
The Slave Address Enable bit controls
whether address matching is performed
in slave mode. When set, the SAEN bit
indicates that the ADDR field holds a
valid address and enables the match of
ADDR to an incoming address byte.
The Own Address field holds the 7-bit
ACCESS.Bus address of this device. In
slave mode, the 7 bits received after a
Start Condition are compared to this field
(first bit received to bit 6, and the last to
bit 0). If the address field matches the
received data and the SAEN bit is set, a
match is detected.
18.0 Memory Map
All RAM, ports and registers (except A and PC) are mapped
into data memory address space.
Address
ADD REG
00 to 6F
70 to 7F
80 to 83
84
85
86
87 to 8F
90 to 93
94
95
96
97
98 to 9F
A0 to A7
Contents
On-Chip RAM bytes (112 bytes)
Unused RAM Address Space (Reads As
All Ones)
Unused RAM Address Space (Reads
Undefined Data)
Port C MIWU Edge Select Register
(Reg: CWKEDG)
Port C MIWU Enable Register (Reg:
CWKEN)
Port C MIWU Pending Register (Reg:
CWKPND)
Reserved
Reserved
Port F Data Register
Port F Configuration Register
Port F Input pins (Read Only)
Reserved for Port F
Reserved
Reserved
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