COP8TAB9 Datasheet, PDF (26/59 Pages) National Semiconductor (TI) – 8-Bit CMOS Flash Microcontroller with 2k Byte or 4k Byte Memory

12.0 Timers (Continued)
12.2 TIMER T1
One of the main functions of a microcontroller is to provide
timing and counting capability for real-time control tasks. The
COP8 family offers a very versatile 16-bit timer/counter
structure, and two supporting 16-bit autoreload/capture reg-
isters (R1A and R1B), optimized to reduce software burdens
in real-time control applications. The timer block has two pins
associated with it, T1A and T1B. Pin T1A supports I/O re-
quired by the timer block, while pin T1B is an input to the
timer block.
The timer block has three operating modes: Processor Inde-
pendent PWM mode, External Event Counter mode, and
Input Capture mode.
The control bits T1C3, T1C2, and T1C1 allow selection of the
different modes of operation.
12.3 MODE 1. PROCESSOR INDEPENDENT PWM
MODE
One of the timer’s operating modes is the Processor Inde-
pendent PWM mode. In this mode, the timer generates a
“Processor Independent” PWM signal because once the
timer is setup, no more action is required from the CPU
which translates to less software overhead and greater
throughput. The user software services the timer block only
when the PWM parameters require updating. This capability
is provided by the fact that the timer has two separate 16-bit
reload registers. One of the reload registers contains the
“ON” timer while the other holds the “OFF” time. By contrast,
a microcontroller that has only a single reload register re-
quires an additional software to update the reload value
(alternate between the on-time/off-time).
The timer can generate the PWM output with the width and
duty cycle controlled by the values stored in the reload
registers. The reload registers control the countdown values
and the reload values are automatically written into the timer
when it counts down through 0, generating interrupt on each
reload. Under software control and with minimal overhead,
the PMW outputs are useful in controlling motors, triacs, the
intensity of displays, and in providing inputs for data acqui-
sition and sine wave generators.
In this mode, the timer T1 counts down at a fixed rate of t_C.
Upon every underflow the timer is alternately reloaded with
the contents of supporting registers, R1A and R1B. The very
first underflow of the timer causes the timer to reload from
the register R1A. Subsequent underflows cause the timer to
be reloaded from the registers alternately beginning with the
register R1B.
The T1 Timer control bits, T1C3, T1C2 and T1C1 set up the
timer for PWM mode operation.
Figure 19 shows a block diagram of the timer in PWM mode.
The underflows can be programmed to toggle the T1A output
pin. The underflows can also be programmed to generate
interrupts.
Underflows from the timer are alternately latched into two
pending flags, T1PNDA and T1PNDB. The user must reset
these pending flags under software control. Two control
enable flags, T1ENA and T1ENB, allow the interrupts from
the timer underflow to be enabled or disabled. Setting the
timer enable flag T1ENA will cause an interrupt when a timer
underflow causes the R1A register to be reloaded into the
timer. Setting the timer enable flag T1ENB will cause an
interrupt when a timer underflow causes the R1B register to
be reloaded into the timer. Resetting the timer enable flags
will disable the associated interrupts.
Either or both of the timer underflow interrupts may be
enabled. This gives the user the flexibility of interrupting
once per PWM period on either the rising or falling edge of
the PWM output. Alternatively, the user may choose to inter-
rupt on both edges of the PWM output.
20047531
FIGURE 19. Timer in PWM Mode
12.4 MODE 2. EXTERNAL EVENT COUNTER MODE
This mode is quite similar to the processor independent
PWM mode described above. The main difference is that the
timer, T1, is clocked by the input signal from the T1A pin. The
T1 timer control bits, T1C3, T1C2 and T1C1 allow the timer
to be clocked either on a positive or negative edge from the
T1A pin. Underflows from the timer are latched into the
T1PNDA pending flag. Setting the T1ENA control flag will
cause an interrupt when the timer underflows.
In this mode the input pin T1B can be used as an indepen-
dent positive edge sensitive interrupt input if the T1ENB
control flag is set. The occurrence of a positive edge on the
T1B input pin is latched into the T1PNDB flag.
Figure 20 shows a block diagram of the timer in External
Event Counter mode.
Note: The PWM output is not available in this mode since the T1A pin is
being used as the counter input clock.
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