COP8TAB9 Datasheet, PDF (36/59 Pages) National Semiconductor (TI) – 8-Bit CMOS Flash Microcontroller with 2k Byte or 4k Byte Memory

14.0 Interrupts (Continued)
user program should contain the Software Trap routine to
perform a recovery procedure rather than a return to normal
execution.
Under normal conditions, the STPND flag is reset by a
RPND instruction in the Software Trap service routine. If a
programming error or hardware condition (brownout, power
supply glitch, etc.) sets the STPND flag without providing a
way for it to be cleared, all other interrupts will be locked out.
To alleviate this condition, the user can use extra RPND
instructions in the main program and in the Watchdog ser-
vice routine (if present). There is no harm in executing extra
RPND instructions in these parts of the program.
FIGURE 27. VIS Flow Chart
20047578
14.4.2.1 Programming Example: External Interrupt
WAIT:
PSW
CNTRL
RBIT
RBIT
SBIT
SBIT
SBIT
JP
.
.
.
.=0FF
VIS
=00EF
=00EE
0,PORTGC
0,PORTGD
IEDG, CNTRL
GIE, PSW
EXEN, PSW
WAIT
.
.
.
.=01FA
.ADDRW SERVICE
.
.
; G0 pin configured Hi-Z
; Ext interrupt polarity; falling edge
; Set the GIE bit
; Enable the external interrupt
; Wait for external interrupt
; The interrupt causes a
; branch to address 0FF
; The VIS causes a branch to
; interrupt vector table
; Vector table (within 256 byte
; of VIS inst.) containing the ext
; interrupt service routine
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