COP8TAB9 Datasheet, PDF (21/59 Pages) National Semiconductor (TI) – 8-Bit CMOS Flash Microcontroller with 2k Byte or 4k Byte Memory

10.0 Functional Description
(Continued)
Carry) instructions will respectively set or clear both the carry
flags. In addition to the SC and RC instructions, ADC, SUBC,
RRC and RLC instructions affect the Carry and Half Carry
flags.
10.8.3 ICNTRL Register (Address X'00E8)
Unused LPEN
Bit 7
T0PND
T0EN µWPND µWEN T1PNDB
T1ENB
Bit 0
The ICNTRL register contains the following bits:
LPEN L/C Port Interrupt Enable (Multi-Input
Wake-Up/Interrupt)
T0PND Timer T0 Interrupt pending
T0EN Timer T0 Interrupt Enable (Bit 12 toggle)
µWPND MICROWIRE/PLUS interrupt pending
µWEN Enable MICROWIRE/PLUS interrupt
T1PNDB Timer T1 Interrupt Pending Flag for T1B capture
edge
T1ENB Timer T1 Interrupt Enable for T1B Input capture
edge
10.8.4 ITMR Register (Address X'00CF)
Bit 7
RSVD
ITSEL2 ITSEL1 ITSEL0
Bit 0
The ITMR register contains the following bits:
RSVD These bits are reserved and must be 0.
ITSEL2 Idle Timer period select bit.
ITSEL1 Idle Timer period select bit.
ITSEL0 Idle Timer period select bit.
11.0 In-System Programming
11.1 INTRODUCTION
This device provides the capability to program the program
memory while installed in an application board. This feature
is called In System Programming (ISP). It provides a means
of ISP by using the MICROWIRE/PLUS, or the user can
provide his own, customized ISP routine. The factory in-
stalled ISP uses the MICROWIRE/PLUS port. The user can
provide his own ISP routine that uses any of the capabilities
of the device, such as ACCESS.Bus, parallel port, etc. The
user is cautioned, however, to remove all calls to Boot ROM
functions prior to submission of code for ROM generation
and production in COP8TAx5 devices.
11.2 FUNCTIONAL DESCRIPTION
The organization of the ISP feature consists of the user
Flash program memory, the factory boot ROM, and some
registers dedicated to performing the ISP function. See Fig-
ure 17 for a simplified block diagram. The factory installed
ISP that uses MICROWIRE/PLUS is located in the Boot
ROM. The size of the Boot ROM is 1k bytes and also
contains code to facilitate in system emulation capability. If a
user chooses to write an application specific ISP routine, it
must be located in the Flash program memory.
20047529
FIGURE 17. Block Diagram of ISP
As described in Section 10.4 OPTION REGISTER, there is a
bit, FLEX, that controls whether the device exits RESET
executing from the Flash memory or the Boot ROM. The
user must program the FLEX bit as appropriate for the
application. In the erased state, the FLEX bit = 0 and the
device will power-up executing from Boot ROM. When FLEX
= 0, this assumes that either the MICROWIRE/PLUS ISP
routine or external programming is being used to program
the device. If using the MICROWIRE/PLUS ISP routine, the
software in the boot ROM will monitor the MICROWIRE/
PLUS for commands to program the Flash memory. When
programming the Flash program memory is complete, the
FLEX bit will have to be programmed to a 1 and the device
will have to be reset, either by pulling external Reset to
ground or by a MICROWIRE/PLUS ISP EXIT command,
before execution from Flash program memory will occur.
If FLEX = 1, upon exiting Reset, the device will begin ex-
ecuting from location 0000 in the Flash program memory.
The assumption, here, is that either the application is not
using ISP, is using MICROWIRE/PLUS ISP by jumping to it
within the application code, or is using a customized ISP
routine. If a customized ISP routine is being used, then it
must be programmed into the Flash memory by means of
the MICROWIRE/PLUS ISP or external programming as
described in the preceding paragraph.
11.3 REGISTERS
There are six registers required to support ISP: Address
Register Hi byte (ISPADHI), Address Register Low byte
(ISPADLO), Read Data Register (ISPRD), Write Data Reg-
ister (ISPWR), Write Timing Register (PGMTIM), and the
Control Register (ISPCNTRL). The ISPCNTRL Register is
not available to the user. None of these six registers, which
support ISP, have been implemented in the COP8TAx5 ROM
based devices.
11.3.1 ISP Address Registers
The address registers (ISPADHI & ISPADLO) are used to
specify the address of the byte of data being written or read.
For page erase operations, the address of the beginning of
the page should be loaded. For mass erase operations,
0000 must be placed into the address registers. When read-
ing the Option register, 07FF (hex) should be placed into the
address registers of COP8TAB9 devices and 0FFF (hex)
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