COP8TAB9 Datasheet, PDF (28/59 Pages) National Semiconductor (TI) – 8-Bit CMOS Flash Microcontroller with 2k Byte or 4k Byte Memory

12.0 Timers (Continued)
12.6 TIMER CONTROL FLAGS
The control bits and their functions are summarized below.
T1C3 Timer mode control
T1C2 Timer mode control
T1C1 Timer mode control
T1C0
Timer Start/Stop control in Modes 1 and 2 (Pro-
cessor Independent PWM and External Event
Counter), where 1 = Start, 0 = Stop
Timer Underflow Interrupt Pending Flag in Mode
3 (Input Capture)
T1PNDA Timer Interrupt Pending Flag
T1ENA Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled
0 = Timer Interrupt Disabled
T1PNDB Timer Interrupt Pending Flag
T1ENB Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled
0 = Timer Interrupt Disabled
The timer mode control bits (T1C3, T1C2 and T1C1) are
detailed below:
Mode
1
2
3
T1C3
1
1
0
0
0
1
0
1
T1C2
0
0
0
0
1
1
1
1
T1C1
1
0
0
1
0
0
1
1
Description
PWM: T1A Toggle
PWM: No T1A
Toggle
External Event
Counter
External Event
Counter
Captures:
T1A Pos. Edge
T1B Pos. Edge
Captures:
T1A Pos. Edge
T1B Neg. Edge
Captures:
T1A Neg. Edge
T1B Neg. Edge
Captures:
T1A Neg. Edge
T1B Neg. Edge
Interrupt A
Source
Autoreload RA
Autoreload RA
Interrupt B
Source
Autoreload RB
Autoreload RB
Timer Underflow Pos. T1B Edge
Timer Underflow Pos. T1B Edge
Pos. T1A Edge
or Timer
Underflow
Pos. T1A
Edge or Timer
Underflow
Neg. T1A
Edge or Timer
Underflow
Neg. T1A
Edge or Timer
Underflow
Pos. T1B Edge
Neg. T1B
Edge
Neg. T1B
Edge
Neg. T1B
Edge
Timer
Counts On
t_C
t_C
Pos. T1A
Edge
Pos. T1A
Edge
t_C
t_C
t_C
t_C
13.0 Power Save Modes
Today, the proliferation of battery-operated based applica-
tions has placed new demands on designers to drive power
consumption down. Battery-operated systems are not the
only type of applications demanding low power. The power
budget constraints are also imposed on those consumer/
industrial applications where well regulated and expensive
power supply costs cannot be tolerated. Such applications
rely on low cost and low power supply voltage derived di-
rectly from the “mains” by using voltage rectifier and passive
components. Low power is demanded even in automotive
applications, due to increased vehicle electronics content.
This is required to ease the burden from the car battery. Low
power 8-bit microcontrollers supply the smarts to control
battery-operated, consumer/industrial, and automotive appli-
cations.
The COP8TAx devices offer system designers a variety of
low-power consumption features that enable them to meet
the demanding requirements of today’s increasing range of
low-power applications. These features include low voltage
operation, low current drain, and power saving features such
as HALT, IDLE, and Multi-Input Wake-Up (MIWU).
The devices offer the user two power save modes of opera-
tion: HALT and IDLE. In the HALT mode, all microcontroller
activities are stopped. In the IDLE mode, the on-board os-
cillator circuitry and timer T0 are active but all other micro-
controller activities are stopped. In either mode, all on-board
RAM, registers, I/O states, and timers (with the exception of
T0) are unaltered.
Clock Monitor if enabled can be active in both modes.
13.1 HALT MODE
The device can be placed in the HALT mode by writing a “1”
to the HALT flag (G7 data bit). All microcontroller activities,
including the clock and timers, are stopped. The WATCH-
DOG logic on the device is disabled during the HALT mode.
However, the clock monitor circuitry, if enabled, remains
active and will cause the WATCHDOG output pin (WDOUT)
to go low. If the HALT mode is used and the user does not
want to activate the WDOUT pin, the Clock Monitor should
be disabled after the device comes out of reset (resetting the
Clock Monitor control bit with the first write to the WDSVR
register). In the HALT mode, the power requirements of the
device are minimal and the applied voltage (V_CC) may be
decreased to V_r (V_r = 2.0V) without altering the state of the
machine.
The device supports three different ways of exiting the HALT
mode. The first method of exiting the HALT mode is with the
Multi-Input Wake-Up feature on Port L and Port C. The
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