COP8TAB9 Datasheet, PDF (18/59 Pages) National Semiconductor (TI) – 8-Bit CMOS Flash Microcontroller with 2k Byte or 4k Byte Memory

10.0 Functional Description
(Continued)
Monitor error following reset if the clock has not reached
the minimum specified frequency at the termination of
reset. A Clock Monitor error will cause an active low output
on pin G1. This error output will continue until 16–32 T0
clock cycles following the clock frequency reaching the
minimum specified value, at which time the G1 output will
go high.
10.6.1 External Reset
The RESET input, when pulled low, initializes the device.
The RESET pin must be held low for a minimum of one
instruction cycle to guarantee a valid reset. An R/C circuit on
the RESET pin with a delay 5 times (5x) greater than the
power supply rise time is recommended. Reset should also
be long enough to ensure crystal start-up upon Power-Up.
RESET may also be used to cause an exit from the HALT
mode.
Note: Flash memory may be non-volatile, but it is not invulnerable. Any
controller which features the capability for the software to modify the
contents of the Flash memory is susceptible to inadvertent writes or
erases any time V_CC is below the minimum guaranteed operating
conditions, the clock is running and the device is not held in Reset. For
this reason, we recommend the use of external brownout detection
any time V_CC drops below the minimum guaranteed V_CC/Frequency
operating conditions.
A recommended reset circuit for this device is shown in
Figure 11.
t_C. After the underflow, the logic is designed such that the
Power On Reset circuit will generate no additional internal
resets as long as V_CC remains above 2.0V.
Note: The POR feature of the COP8TAB9/TAC9 is not intended to function as
a brownout detector. A brownout condition is reached whenever VCC
of the device goes below the minimum guaranteed operating condi-
tions. The minimum guaranteed operating conditions are defined in the
Electrical Specifications. We strongly recommend the use of an exter-
nal supervisory circuit which ensures that the COP8 device is held in
the RESET state until Vcc has recovered to the minimum operating
conditions as stated above.
The contents of data registers and RAM are unknown fol-
lowing the on-chip reset.
20047522
FIGURE 11. Reset Circuit Using External Reset
10.6.2 On-Chip Power-On Reset
The device generates an internal reset as V_CC rises to a
voltage level above 2.0V. The on-chip reset circuitry is able
to detect both fast and slow rise times on V_CC (V_CC rise time
between 20 µs and 10 ms).
Under no circumstances should the RESET pin be allowed
to float. If the on-chip Power-On Reset feature is being used,
RESET pin should be connected to V_CC , either directly or
through a pull-up resistor. If forced operation from the Boot
ROM is anticipated, a pull-up resistor should always be used
so that the ISP circuit can override the RESET circuit and
force the RESET pin low. The output of the power-on reset
detector will always preset the Idle timer to 00FF(256 t_C). At
this time, the internal reset will be generated.
The internal reset will not be turned off until the Idle timer
underflows. The internal reset will perform the same func-
tions as external reset. The user is responsible for ensuring
that V_CC is at the minimum level for operating within the 256
20047523
FIGURE 12. Reset Timing (Power-On Reset Enabled)
with V_CC Tied to RESET
10.7 OSCILLATOR CIRCUITS
There are five clock oscillator options available: fully internal
R/C Oscillator, R/C Oscillator with external frequency deter-
mination resistor, Crystal Oscillator with or without on-chip
bias resistor and External Oscillator. The oscillator feature is
selected by programming the Option Byte, which is summa-
rized in Table 2.
TABLE 2. Oscillator Option
Option
Bit 6
0
0
0
0
1
Option
Bit 4
0
0
1
1
x
Option
Bit 3
Oscillator Option
0 On-Chip R/C Oscillator
1 R/C Oscillator with External Resistor
0 Crystal Oscillator with Internal Bias
Resistor
1 Crystal Oscillator with External Bias
Resistor
x External Oscillator
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