COP8TAB9 Datasheet, PDF (11/59 Pages) National Semiconductor (TI) – 8-Bit CMOS Flash Microcontroller with 2k Byte or 4k Byte Memory

8.0 Electrical Characteristics (Continued)
AC Electrical Characteristics −40˚C ≤ T_A ≤ +85˚C unless otherwise specified.
Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Parameter
Conditions
Min
Typ
Oscillator Frequency
Crystal/Resonator, External
Internal R/C Oscillator
R/C Oscillator Frequency Variation
Instruction Cycle Time (t_C)
Crystal/Resonator, External
Internal R/C Oscillator
External CKI Clock Duty Cycle
2.25V ≤ V_CC ≤ 2.75V
2.25V ≤ V_CC ≤ 2.75V
2.25V ≤ V_CC ≤ 2.75V
2.25V ≤ V_CC ≤ 2.75V
2.25V ≤ V_CC ≤ 2.75V
fr = Max
9.0
0.65
1.1
45
Rise Time
fr = 10 MHz Ext Clock
Fall Time
fr = 10 MHz Ext Clock
MICROWIRE Setup Time (t_UWS) Figure 1
20
MICROWIRE Hold Time (t_UWH) Figure 1
20
MICROWIRE Output Propagation Delay (t_UPD) Figure
1
MICROWIRE Maximum Shift Clock
Master Mode
Slave Mode
Input Pulse Width
Interrupt Input High Time (Note 2)
1
Interrupt Input Low Time
1
Timer Input High Time
1
Timer Input Low Time
1
Reset Pulse Width
0.5
Mass Erase Time
200
Page Erase Time
20
ACCESS.Bus Input signals (Note 6)
Bus Free Time Between Stop and Start Condition
(t_BUFi) Figure 2
SCL Setup Time (t_CSTOsi) Figure 2
SCL Hold Time (t_CSTRhi) Figure 2
SCL Setup Time (t_CSTRsi) Figure 3
Data High Setup Time (t_DHCsi) Figure 3
Data Low Setup Time (t_DLCsi) Figure 2
SCL Low Time (t_SCLlowi) Figure 4
SCL High Time (t_SCLhighi) Figure 4
SDA Hold Time (t_SDAhi) Figure 4
SDA Setup Time (t_SDAsi) Figure 4
ACCESS.Bus Output Signals (Note 6)
t_SCLhigho
Before Stop Condition
8
After Start Condition
8
Before Start Condition
8
Before SCL Rising Edge (RE)
2
Before SCL RE
2
After SCL Falling Edge (FE)
12
After SCL RE
12
After SCL FE
0
Before SCL RE
2
Bus Free Time Between Stop and Start Condition
(t_BUFo) Figure 2
SCL Setup Time (t_CSTOso) Figure 2
SCL Hold Time (t_CSTRho) Figure 3
SCL Setup Time (t_CSTRso) Figure 3
Data High Setup Time (t_DHCso) Figure 3
Data Low Setup Time (t_DLCso) Figure 2
SCL Low Time (t_SCLlowo) Figure 4
SCL High Time (t_SCLhigho) Figure 4
Before Stop Condition
After Start Condition
Before Start Condition
Before SCL RE
Before SCL RE
After SCL FE
After SCL RE
t_SCLhigho
t_SCLhigho
t_SCLhigho
t_SCLhigho
t_SCLhigho
t_SCLhigho
16
16
Max
15
±30
DC
55
12
8
150
750
1.5
Units
MHz
MHz
%
µs
µs
%
ns
ns
ns
ns
ns
kHz
MHz
t_C
t_C
t_C
t_C
µs
ms
ms
mclk
mclk
mclk
mclk
mclk
mclk
mclk
ns
mclk
mclk
mclk
11
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