COP8TAB9 Datasheet, PDF (2/59 Pages) National Semiconductor (TI) – 8-Bit CMOS Flash Microcontroller with 2k Byte or 4k Byte Memory

3.0 Block Diagram
20047501
4.0 Ordering Information
COP8
TA
Family and
Feature Set
Indicator
C
Program
Memory
Size
B = 2k
C = 4k
Part Numbering Scheme
9
H
Program
Memory
No. Of Pins
Type
5 = Masked ROM C = 20 Pin
9 = Flash
E = 28 Pin
H = 44 Pin
LQ
Package
Type
LQ = LLP
MW = SOIC WIDE
8
Temperature
8 = -40 to +85˚C
Note: The user, utilizing the COP8TAx9 Flash based devices during devel-
opment for applications to be produced using the COP8TAx5 ROM
devices, is cautioned to ensure that code contains NO calls to Boot
ROM functions prior to submission for ROM generation. Instances of
the JSRB instruction in ROM based devices will be executed as a JSR
instruction to a location in the first 256 bytes of Program Memory.
Flash and ROM devices are not 100% identical. The execution of the
JSRB instruction is an example of the potential differences between
the devices. For this reason, the user is strongly advised to obtain a
masked ROM prototype devices before committing to production
quantities. This will allow the user to ensure there are no unexpected
differences between Flash an ROM devices within the application.
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