COP8TAB9 Datasheet, PDF (20/59 Pages) National Semiconductor (TI) – 8-Bit CMOS Flash Microcontroller with 2k Byte or 4k Byte Memory

10.0 Functional Description (Continued)
With External Frequency Control Resistor (R/C+R)
With Fully On-Chip R/C Oscillator.
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FIGURE 16. R/C Oscillator
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10.7.2 Crystal Oscillator
The Crystal Oscillator mode can be selected by program-
ming Option Bit 4 to 1. CKI is the clock input while G7/CKO
is the clock generator output to the crystal. An on-chip bias
resistor connected between CKI and CKO can be enabled
by programming Option Bit 3 to 0. The value of the resistor is
in the range of 0.3M to 2.5M (typically 1.0M).
Table 4 shows the component values required for various
standard crystal values. Resistor R2 is only used when the
on-chip bias resistor is disabled. Figure 13 and Figure 14
show the crystal oscillator connection diagrams.
TABLE 4. Crystal Oscillator Configuration,
T_A = 25˚C, V_CC = 2.5V
R1 (kΩ) R2 (MΩ) C1 (pF) C2 (pF) CKI Freq. (MHz)
0
1
18
18
15
0
1
18
18
10
0
1
45 30–36
4
5.6
1
100 100–156
0.455
10.7.3 External Oscillator
The External Oscillator mode can be selected by program-
ming Option Bit 3 to 0 and Option Bit 4 to 0. CKI can be
driven by an external clock signal provided it meets the
specified duty cycle, rise and fall times, and input levels.
G7/CKO is available as a general purpose input G7 and/or
Halt control. Figure 13 shows the external oscillator connec-
tion diagram.
10.7.4 Clock Prescaler
The device is equipped with a programmable clock prescaler
which allows the user to dynamically adjust the clock speed,
and thus the power dissipation, to the processing needs of
the application. By merely writing an eight-bit value to the
CLKPS register, the user can divide the input oscillator clock
by an integer multiple (1 — 256) and reduce the CPU clock
frequency. The format of the CLKPS Register is shown in
Table 5. The value written to the CLKPS register is one less
than the desired divider. A value of 0 (zero) written to the
CLKPS register yields a CPU clock equal to the input clock
frequency. A value of 255 written to the CLKPS register
yields a CPU clock with a period equal to 256 input clock
periods.
TABLE 5. Clock Prescale Register (CLKPS)
Bit 7
CLKPS
Bit 0
10.8 CONTROL REGISTERS
10.8.1 CNTRL Register (Address X'00EE)
T1C3 T1C2 T1C1 T1C0 MSEL IEDG
SL1
Bit 7
SL0
Bit 0
The Timer1 (T1) and MICROWIRE/PLUS control register
contains the following bits:
T1C3
Timer T1 mode control bit
T1C2
Timer T1 mode control bit
T1C1
Timer T1 mode control bit
T1C0
Timer T1 Start/Stop control in timer
modes 1 and 2. T1 Underflow Interrupt
Pending Flag in timer mode 3
MSEL
Selects G5 and G4 as MICROWIRE/PLUS
signals SK and SO respectively
IEDG
External interrupt edge polarity select
(0 = Rising edge, 1 = Falling edge)
SL1 & SL0 Select the MICROWIRE/PLUS clock divide
by (00 = 2, 01 = 4, 1x = 8)
10.8.2 PSW Register (Address X'00EF)
HC
Bit 7
C T1PNDA T1ENA
EXPND
BUSY
EXEN
GIE
Bit 0
The PSW register contains the following select bits:
HC
Half Carry Flag
C
Carry Flag
T1PNDA Timer T1 Interrupt Pending Flag (Autoreload RA
in mode 1, T1 Underflow in Mode 2, T1A capture
edge in mode 3)
T1ENA Timer T1 Interrupt Enable for Timer Underflow
or T1A Input capture edge
EXPND External interrupt pending
BUSY MICROWIRE/PLUS busy shifting flag
EXEN Enable external interrupt
GIE
Global interrupt enable (enables interrupts)
The Half-Carry flag is also affected by all the instructions that
affect the Carry flag. The SC (Set Carry) and RC (Reset
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