PC87591E Datasheet, PDF (395/437 Pages) National Semiconductor (TI) – LPC Mobile Embedded Controllers

7.0 Device Specifications (Continued)
7.6.8 PS/2 Interface Timing
Symbol Figure
Description
Reference Conditions
Min
Max
Unit
PS/2 Input Timing
t_PSDIs
144 Input setup time PSDAT1-3 Before FE PSCLK1-3
0
ns
t_PSDIh
144 Input hold time PSDAT1-3 After RE PSCLK1-3
0
ns
t_PSCLKl
144 PSCLK1-3 low time
At 0.8V (Both Edges)
(n+1)t_CLK1 ns
-
t_PSCLKh
144 PSCLK1-3 high time
At 2.0V (Both Edges)
(n+1)t_CLK1 ns
-
PS/2 Output Timing
t_PSDOv
145 Output valid time
PSDAT1-4
After FE PSCLK1-4
(n + 6) _* t_CLK
-
+ 14² ns
t_PSDOh
145 Output hold time PSDAT1-4 After FE PSCLK1-4
0
ns
t_PSCLKa
146 Output active time PSCLK1-4 After RE CLK
17
ns
t_PSCLKia
146 Output inactive time
PSCLK1-4
After RE CLK
17
ns
1. ‘n’ is the number of clock cycles, as programed in the IDB field. See “PS/2 Control Register (PSCON)” on
page 130.
2. ‘n’ is defined in “PS/2 Control Register (PSCON)” on page 130.
PSCLK1-4
t_PSCLKl
t_PSCLKh
PSDAT1-4
t_PSDIs
t_PSDIh
Figure 144. PS/2 Receive Timing
Revision 1.07
395
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