PC87591E Datasheet, PDF (313/437 Pages) National Semiconductor (TI) – LPC Mobile Embedded Controllers

Host Controller Interface Modules (Continued)
5.4 CORE ACCESS TO HOST-CONTROLLED MODULES
The PC87591x enables the core to access the Host-Controlled module registers (e.g., host configuration module, RTC and
MSWC), using the SuperI/O Internal Bus (SIB) controller.
Host-Controlled Modules Register Arbitration. Since the host processor software and the PC87591x firmware cannot ac-
cess a Host-Controlled module simultaneously, they must communicate to prevent conflicts in Host-Controlled module reg-
ister usage.
Access to the Host-Controlled modules is controlled via a lock bit for each module. When the relevant lock bit is cleared,
access to the Host-Controlled modules registers by the host processor is enabled. When the relevant lock bit is set, access
to the Host-Controlled module registers by the host processor is blocked (i.e., write operations are ignored and read opera-
tions return 00₁₆). Any attempt by the host to access the locked register is flagged by setting the respective bit in SIOLV
register.
SIB Arbitration. The host and core should access the Host-Controlled modules only after preventing host access to the
module (using lock bits, as explained in the previous paragraph). The SIB controller arbitrates SIB usage between the host
and core. If a core transaction starts after an LPC transaction has started, it waits for the completion of the LPC transaction.
If a core transaction starts before an LPC transaction starts, the core transaction finishes before handling the LPC transac-
tion.
The PC87591x firmware may access the Host-Controlled modules only while the core domain is in Active mode, the Host
Domain power plane is on and the host domain clock is enabled with a minimum operation frequency of TBD.
Core Read Operation. To perform a read operation by the core from a Host-Controlled module register:
1. Set CSAE bit in SIBCTRL register, if not already set.
2. Verify that both CSRD and CSWR bits in SIBCTRL register are cleared.
3. Select the device to be accessed by setting its respective bit in CRSMAE register, if not already set. All other bits in the
register must be cleared.
4. Specify the offset of the register in the device in IHIOA register, if not already specified.
5. Write 1 to CSRD bit in SIBCTRL register.
6. Read the CSRD bit in SIBCTRL until it returns 0.
7. Read the data from IHD register.
Core Write Operation. To perform a write operation by the core from a Host-Controlled module register:
1. Set CSAE bit in SIBCTRL register, if not already set.
2. Verify that both CSRD and CSWR bits in SIBCTRL register are cleared.
3. Select the device to be accessed by setting its respective bit in CRSMAE register, if not already set. All other bits in the
register must be cleared.
4. Specify the offset of the register in the device in IHIOA register, if not already specified.
5. Write the data to IHD register; this starts the write operation to the device.
6. Read the CSWR bit in SIBCTRL until it returns 0; this indicates the completion of the write transaction.
The following sequence is provided for minimal conflict between host and core in the use of Host-Controlled peripherals.
1. After arbitrating the use of the specific Host-Controlled modules with the host, set the corresponding lock bit (see
LKSIOHA register).
2. Read and save all Host-Controlled module registers required for proper operation of the host. Beware of destructive
reads.
3. After the Host-Controlled module access is complete, restore the Host-Controlled module registers saved in step 2.
4. Clear the corresponding lock bit to allow the host to access the Host-Controlled module.
When accessing the RTC, also:
1. To access locked memory locations in the RTC, set (1) RTCMR bit in SIBCTRL register to clear the RTC lock bits.
2. Access the RTC’s CMOS-RAM and its registers. To prevent conflicts with the host software, the firmware should not read
any of the RTC read-volatile registers.
3. After the RTC access is complete, if the RTC locking was removed, re-lock the RTC memory and restore the RTC mem-
ory bank selection and the address pointer.
Revision 1.07
313
www.national.com