PC87591E Datasheet, PDF (273/437 Pages) National Semiconductor (TI) – LPC Mobile Embedded Controllers

Embedded Controller Modules (Continued)
4.20.5 Freezing Events
The PC87591x can prevent real-time events from interfering with the operation of the ADB monitor and changing the status
of the PC87591x. This is done by disabling maskable interrupts and setting FREEZE bit; the FREEZE bit freezes the
WATCHDOG counter and disables destructive read operations.
Disabling Maskable Interrupts
Clearing the core I or E bits in PSR register disables the maskable interrupts. The I bit is cleared automatically whenever a
trap or interrupt occurs and after reset.
Freezing the WATCHDOG Counter
To freeze the WATCHDOG counter, FREEZE bit in DBGCFG register must be set to 1 on entering a TMON routine (the bit
must be cleared before returning to the application). Setting FREEZE bit prevents the WATCHDOG from generating the re-
set that occurs if WATCHDOG is not cleared on time (see Section 4.10 on page 164). The WATCHDOG counter keeps its
value while it is frozen and resumes counting after FREEZE is cleared.
If an application fails to touch the WATCHDOG in time and a reset event is generated before or while FREEZE bit is set, the
PC87591x receives the reset.
Disabling Additional Modules
The two MFT16 and the two ACB modules may be frozen by the FREEZE bit. Freezing is enabled when the respective bit
in DBGFRZEN register is set; the bits can be set to meet specific needs of different applications.
Disabling Destructive Reads
When FREEZE in DBGCFG register is set (1), destructive reads do not change the system state (i.e., they return the read
data but do not clear or set bits or send signals). This allows the debugger to present the values of these bits. NMISTAT is
an exception to this rule and is not affected by FREEZE. Core accesses to Host domain registers (using the “Core Access
to Host Controlled Modules”) may also be destructive but are not affected by FREEZE. Note that host operations continue
without any FREEZE bit impact.
4.20.6 Monitoring Activity During Development
In DEV environment, information is available for monitoring on-chip activities and implementing debug features in the devel-
opment system.
Bus Status Signals
The Bus Status signals (BST2-0) indicate if a transaction on the core bus was issued and, if so, the type of transaction.
The BST2-0 signals reflect activity on the core bus. For word accesses involving 8-bit expansion memory, the core bus cycle
triggers two external bus cycles. The first external bus cycle is flagged as a T1 cycle of the core bus. The second is not
flagged as a T1 cycle, i.e., BST2-0 is 000. See Table 41.
Table 41. Core Bus Transaction Encoding
BST
Core Bus Transaction Type
000 Not a T1 cycle, except when the core waits for an
interrupt following WAIT instruction execution
001 Core waits for an interrupt following WAIT
instruction execution
010 T1 of an interrupt acknowledge bus cycle
011 T1 of a data transfer of a non-core bus master
100 T1 of a sequential instruction fetch
101 T1 of a non-sequential instruction fetch
110 T1 of a core data transfer
111 T1 of an exception data transfer
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