PC87591E Datasheet, PDF (155/437 Pages) National Semiconductor (TI) – LPC Mobile Embedded Controllers

Embedded Controller Modules (Continued)
1
START
BIT
1a
START
BIT
1b
START
BIT
1c
START
BIT
7-BIT DATA
7-BIT DATA
7-BIT DATA
7-BIT DATA
S
2S
PA S
PA
2S
Figure 55. Seven Data Bit Frame Options
The format shown in Figure 56 consists of one start bit, eight data bits (excluding parity) and one or two stop bits. If parity
bit generation is enabled by setting the PEN bit, a parity bit is generated and transmitted following the eight data bits.
2
START
BIT
2a
START
BIT
2b
START
BIT
8-BIT DATA
8-BIT DATA
8-BIT DATA
S
2S
PA S
2c
START
BIT
8-BIT DATA
PA
2S
Figure 56. Eight Data Bit Frame Options
The format shown in Figure 57 consists of one start bit, nine data bits and one or two stop bits. This format also supports
the USART attention feature. When operating in this format, all eight bits of UTBUF and URBUF are used for data. The ninth
data bit is transmitted and received using two bits in the control registers, called STPXB9 and RB9. Parity is not generated
or verified in this mode.
3
START
BIT
9-BIT DATA
S
3a
START
BIT
9-BIT DATA
2S
Figure 57. Nine Data Bit Frame Options
Baud Rate Generator
The Baud Rate Generator provides the basic baud clock from the system clock. The system clock is passed through a two-
stage divider chain consisting of a 5-bit baud rate pre-scaler (PSC) and an 11-bit baud rate divisor (DIV).
The correspondences between the 5-bit pre-scaler select (PSC) and pre-scaler factors are shown in Table 21.
Revision 1.07
155
www.national.com