PC87591E Datasheet, PDF (332/437 Pages) National Semiconductor (TI) – LPC Mobile Embedded Controllers

Host Controller Interface Modules (Continued)
Bit
Name
Reset
7
6
5
EICFGPSO EICFGPBM EIACPIS5
0
0
0
4
EIACPIS4
0
3
EIACPIS3
0
2
EIACPIS2
0
1
EIACPIS1
0
0
EIRTCAL
0
Bit
Description
0 EIRTCAL (Enable Interrupt on RTC Alarm). Mask generation of interrupt to the core on setting of the RTC
Alarm bit in MSWCTL1 register.
0: Interrupt disabled (default)
1: Generate a level high interrupt when the RTC Alarm bit is set
5-1 EIACPIS5-1 (Enable Interrupt ACPI request for S5 through S1). Mask generation of interrupt to the core on
changes to ACPISi (i=5-1) bit in MSWCTL2 register. An interrupt enable for ACPIS0 is enabled when any of
these bits is set.
0: Interrupt disabled (default)
1: Generate a level high interrupt on any change to the ACPISi bit
6 EICFGPBM (Enable Interrupt SuperI/O Configuration Register D Power Button Mode). Mask generation of
interrupt to the core on changes to CFGPBM bit in MSWCTL2 register.
0: Interrupt disabled (default)
1: Generate a level high interrupt on any change to the CFGPBM bit
7 EICFGPSO (Enable Interrupt SuperI/O Configuration Register D Power Supply Off). Mask generation of
interrupt to the core on changes to CFGPSO bit in MSWCTL2 register.
0: Interrupt disabled (default)
1: Generate a level high interrupt on any change to the CFGPBM bit
MSWC Host Event Status Register 0 (MSHES0)
This register holds information similar to that in WK_STS0 register. The same event that causes a WK_STS0 bit to be set
sets the respective bit in MSHES0 register. Clearing bits is done for each of the status registers separately. This register is
reset to 00₁₆ on V_CC power-up or Host Domain Software reset. Writing 1 to a bit clears it to 0. Writing 0 has no effect. Bit 6
of this register behaves in a special way on set and clear, as described below.
Location: Offset 00 FCCE₁₆
Type: R/W1C
Bit
Name
Reset
7
6
Module IRQ Software
Event
Event
Status
Status
0
0
5
4
Reserved
0
0
3
RING
Event
Status
0
2
Reserved
0
1
RI2
Event
Status
0
0
RI1
Event
Status
0
Bit
0 RI1 Event Status.
0: Event not detected (default)
1: Event detected
1 RI2 Event Status.
0: Event not detected (default)
1: Event detected
2 Reserved.
Description
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Revision 1.07