PC87591E Datasheet, PDF (362/437 Pages) National Semiconductor (TI) – LPC Mobile Embedded Controllers

Host-Controlled Modules and Host Interface (Continued)
6.2.12 Oscillator Activity
The RTC oscillator is active if:
● _{VCC power supply is higher than VCCON, independent of the battery voltage, VBAT.}
● _{VBAT power supply is higher than VBATMIN whether or not VCC is present.}
The RTC oscillator is disabled in the following cases:
● _{During power-down (VBAT only), if the battery voltage drops below VBATMIN, the PC87591x may enter Battery Fail}
state. In this case, the oscillator may stop oscillating and memory contents may be corrupted or lost.
● _{Software wrote 00X to DV2-0 bits of CRA register and VCC is removed. This disables the oscillator and decreases}
the power consumption from the battery connected to the V_BAT pin. When disabling the oscillator, the CMOS RAM is
not affected as long as the battery is present at a correct voltage level.
If the RTC oscillator becomes inactive, the following features are dysfunctional/disabled:
● _Timekeeping
● _{Periodic interrupt}
● _Alarm
6.2.13 Interrupt Handling
The RTC has a single Interrupt Request line, which handles the following three interrupt conditions:
● _{Periodic interrupt}
● _{Alarm interrupt}
● _{Update end interrupt}
The interrupts are generated if the respective enable bits in CRB register are set prior to an interrupt event occurrence.
Reading the CRC register clears all interrupt flags. Therefore, when multiple interrupts are enabled, the interrupt service
routine should first read and store the CRC register and then deal with all pending interrupts by referring to this stored status.
If an interrupt is not serviced before a second occurrence of the same interrupt condition, the second interrupt event is lost.
Figure 121 illustrates the interrupt timing in the RTC.
Bit 7
of CRA
Bit 4
of CRC
Bit 6
of CRC
Bit 5
of CRC
244 µs
A
P
P/2
B
30.5 µs
P/2
C
Flags (and IRQ) are reset at the conclusion of CRC read
or by reset.
A = Update In Progress bit high before
update occurs = 244 µs
B = Periodic interrupt to update
= Period (periodic int) / 2 + 244 µs
C = Update to Alarm Interrupt = 30.5 µs
P = Period is programed by RS3-0 of CRA
Figure 121. Interrupt/Status Timing
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Revision 1.07