PC87591E Datasheet, PDF (17/437 Pages) National Semiconductor (TI) – LPC Mobile Embedded Controllers

Table of Contents (Continued)
5.3.4
5.3.5
5.3.6
5.3.7
5.3.8
5.3.9
5.3.10
Locking Between Domains ........................................................................................ 300
Host Access Protection ............................................................................................. 301
Response to a Restricted Access ...................................................................... 302
Random Number Generator (PC87591S) ................................................................. 303
Signaling Interface ..................................................................................................... 303
Shared Memory Host Registers ................................................................................ 303
Shared Memory Indirect Memory Address Register 0 (SMIMA0) ...................... 304
Shared Memory Indirect Memory Address Register 1 (SMIMA1) ...................... 304
Shared Memory Indirect Memory Address Register 2 (SMIMA2) ...................... 304
Shared Memory Indirect Memory Address Register 3 (SMIMA3) ...................... 304
Shared Memory Indirect Memory Data Register (SMIMD) ................................ 305
Shared Memory Host Control Register (SMHC) ................................................ 305
Shared Memory Host Status Register (SMHST) ............................................... 305
Shared Memory Host Access Protect Register 1 and 2 (SMHAP1-2) ............... 306
Shared Memory Host Semaphore Register (SMHSEM) .................................... 306
Shared Memory Core Registers ................................................................................ 307
Shared Memory Core Control and Status Register (SMCCST) ......................... 307
Shared Memory Core Top Address Register (SMCTA) ..................................... 308
Shared Memory Host Semaphore Register (SMHSEM) .................................... 308
Shared Memory Core Override Read Protect Registers 0-2 (SMCORP0-2) ..... 309
Shared Memory Core Override Write Protect Registers 0-2 (SMCOWP0-2) .... 310
Random Number Generator Control/Status Register, RNGCS (PC87591S) .... 311
Random Number Generator Data Register, RNGD (PC87591S) ...................... 312
Usage Hints ............................................................................................................... 312
5.4 CORE ACCESS TO HOST-CONTROLLED MODULES ......................................................... 313
5.4.1 Core Access to Host-Controlled Module Registers ................................................... 314
Indirect Host I/O Address Register (IHIOA) ....................................................... 314
Indirect Host Data Register (IHD) ...................................................................... 314
Lock SuperI/O Host Access Register (LKSIOHA) ............................................. 315
SuperI/O Access Lock Violation Register (SIOLV) ............................................ 315
Core to SIB Modules Access Enable Register (CRSMAE) ................................ 316
SIB Control Register (SIBCTRL) ....................................................................... 317
5.5 MOBILE SYSTEM WAKE-UP CONTROL (MSWC) ................................................................ 318
5.5.1 Features .................................................................................................................... 318
5.5.2 Wake-Up Event Detection and Status Bits ................................................................ 318
5.5.3 Wake-Up Output Events ............................................................................................ 320
5.5.4 Other MSWC Controlled Elements ............................................................................ 322
Host Configuration Address Selection ............................................................... 322
Host Keyboard Fast Reset ................................................................................. 322
GA20 Pin Functionality ...................................................................................... 322
5.5.5 MSWC Host Registers ............................................................................................... 323
MSWC Host Register Map ................................................................................. 323
Wake-Up Event Status Register 0 (WK_STS0) ................................................. 323
Wake-Up Events Enable Register (WK_EN0) ................................................... 324
Wake-Up Configuration Register (WK_CFG) .................................................... 325
Wake-Up Signals Value Register (WK_SIGV) ................................................... 325
Wake-Up ACPI State Register (WK_STATE) .................................................... 326
Wake-Up Event Routing to SMI Enable Register 0 (WK_SMIEN0) ................... 327
Wake-Up Event Routing to IRQ Enable Register 0 (WK_IRQEN0) ................... 328
5.5.6 MSWC Core Registers .............................................................................................. 328
Revision 1.07
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