PC87591E Datasheet, PDF (344/437 Pages) National Semiconductor (TI) – LPC Mobile Embedded Controllers

6.0 Host-Controlled Modules and Host Interface (Continued)
Table 55. SuperI/O Configuration Registers (Continued)
Index Mnemonic
Register Name
2A₁₆ - 2C₁₆ Reserved exclusively for National use
2D₁₆ SIOCFD SuperI/O Configuration D
2E₁₆ Reserved exclusively for National use
Power Well
V_PP
Type
R/W
SuperI/O ID Register (SID)
This register contains the identity number of the chip. The PC87591x is identified by the value EC₁₆.
Location: Index 20₁₆
Type: RO
Bit
Name
7
6
5
4
3
2
1
0
Family ID
Reset
EC₁₆
Bit
Description
7-0 Family ID. These bits identify a family of devices with similar functionality but with different options
implemented.
SuperI/O Configuration 1 Register (SIOCF1)
Location: Index 21₁₆
Type: Varies per bit
Bit
Name
7
6
Reserved
5
4
Number of DMA Wait
States
Reset
0
0
0
1
3
2
Number of I/O Wait
States
0
0
1
Software
Reset
0
0
SuperI/O
Devices
Enable
1
Bit Type
Description
0
R/W SuperI/O Devices Enable. Controls the function enable of all the PC87591x SuperI/O logical devices,
except shared memory and Mobile System Wake-Up Control (MSWC). This bit enables the
simultaneous disabling of these modules using a write to a single bit.
0: All SuperI/O logical devices in the PC87591x are disabled, except MSWC and shared memory
1: Each SuperI/O logical device is enabled according to its Activate register (Index 30₁₆) (default)
1
WO Software Reset. Read always returns 0.
0: Ignored (default)
1: Triggers the Host Domain Software Reset event, which resets the logical devices (see Section 6.1.3
on page 341)
3-2 R/W Number of I/O Wait States.
Bits
3 2 Number
0 0: 0 (default)
0 1: 2
1 0: 6
1 1: 12
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Revision 1.07