PC87591E Datasheet, PDF (119/437 Pages) National Semiconductor (TI) – LPC Mobile Embedded Controllers

Embedded Controller Modules (Continued)
When the signal’s direction is set as output (1), a value of 0 is forced. When the direction is set for input (0), the signal is in
TRI-STATE and is not forced low.
4.5.6 GPIO Port Registers
For a summary of the abbreviations used for Register Type, see “Register Abbreviations and Access” on page 34.
GPIO Register Map
Mnemonic
Register Name
PxALT
PyALT
PzALT
PxDIR
PwDIR
PxDOUT
PzDOUT
PwDOUT
PxDIN
PyDIN
PwDIN
PxWPU
PyWPU
Port Px Alternate Function
Port Py Alternate Function
Port Pz Alternate Function
Port Px Direction
Port Pw Direction
Port Px Data Output
Port Pz Data Output
Port Pw Data Output
Port Px Data Input
Port Py Data Input
Port Pw Data Input
Px Weak Pull-Up
Py Weak Pull-Up
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
R/W
R/W
Port Alternate Function Registers (PxALT, PyALT and PzALT)
These registers control the use of each of the Px, Py and Pz pins, respectively, as GPIO ports or as alternate functions.
● _{When cleared (0), each bit in PxALT, PyALT or PzALT enables the corresponding pin as a GPIO signal.}
● _{When set (1), each bit enables the corresponding pin as an alternate function.}
These registers are cleared (0) on reset, except when otherwise noted in Appendix A on page 408.
Location: See Appendix A
Type: R/W
Bit
Name
Reset
7
6
5
4
3
2
1
0
Px Pins Alternate Function Enable
0
0
0
0
0
0
0
0
Bit
Name
Reset
7
6
5
4
3
2
1
0
Py Pins Alternate Function Enable
0
0
0
0
0
0
0
0
Bit
Name
Reset
7
6
5
4
3
2
1
0
Pz Pins Alternate Function Enable
0
0
0
0
0
0
0
0
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