PC87591E Datasheet, PDF (231/437 Pages) National Semiconductor (TI) – LPC Mobile Embedded Controllers

Embedded Controller Modules (Continued)
Flash Memory Status Register (FLSR)
This register provides the on-chip flash status. It is cleared (00₁₆) on reset.
Location: 00 F8C2₁₆
Type: Varies per bit
Bit
Name
Reset
7
6
5
Reserved
0
0
0
4
DERR
0
3
FMLFULL
0
2
FMBUSY
0
1
PERR
0
0
EERR
0
Bit Type
Description
0 R/W1C EERR (Erase Error). Indicates an error in erasing the flash by the core. It is cleared by writing 1 to it.
Writing 0 is ignored. This bit may be cleared only when the FMBUSY bit is cleared (0).
0: No program error detected (default)
1: An error occurred during erase
1 R/W1C PERR (Program Error). Indicates an error in writing to the flash by the core. It is cleared by writing 1
to it. Writing 0 is ignored. This bit may be cleared only when the FMBUSY bit is cleared (0).
0: No program error detected (default)
1: An error occurred during program
2 RO FMBUSY.
0: The embedded flash is ready to accept operations
1: The embedded flash is not accessible since the PC87591x clocks are not ready or the embedded flash
is busy programing or erasing
3 RO FMLFULL (Double-Buffer Full). Indicates that the core can not write to the flash since its buffer is full.
0: There is at least one word empty in the flash double buffer. If IENPROG is set (1), in the Flash Memory
Control register, an interrupt request to the ICU is active.
1: The double-buffer is full
4 R/W1C DERR (Data Loss Error). Indicates that a double-buffer overrun error has occurred during core access.
It is cleared by writing 1 to the DERR bit. Writing 0 is ignored. This bit may be cleared only when the
FMBUSY bit is cleared (0).
0: No data loss detected (default)
1: A write to a full buffer was detected
7-5
Reserved.
Flash Memory Pre-Scaler Register (FLPSLR)
The FLPSLR register selects the pre-scaler divider ratio. FLPSLR defaults to (00₁₆) on reset.
Location: 00 F8C4₁₆
Type: R/W
Bit
Name
Reset
7
6
5
4
3
2
1
0
Reserved
FTDIV
0
0
0
0
0
0
0
0
Bit
Description
3-0 FTDIV (Pre-Scaler Divider Value). This register should be configured based on the currently set core
frequency. See Table 33 on page 223 for details of required values.
7-4 Reserved.
Revision 1.07
231
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