PC87591E Datasheet, PDF (249/437 Pages) National Semiconductor (TI) – LPC Mobile Embedded Controllers

Embedded Controller Modules (Continued)
The TAP block has an IEEE 1149.1b 1994 standard interface to a JTAG serial bus. In addition, it uses TINT to notify the
host/debugger that a message is waiting upstream. The TAP and the JTAG form the debugging communication channel and
port for the PC87591x. They operate as follows:
● _{The TAP copies downstream messages (from the debugger to one of the on-chip processors) to the Rx data link, to}
be read by the relevant processor via the peripheral bus.
● _{A processor writes upstream messages (from an on-chip processor to its debugger) to the Tx data link for upstream}
transmission via the JTAG serial bus.
● _{The ISE interrupt control generates ISE interrupts to the processor in cases of ABORT or a waiting message in the}
Rx data link.
● _{The debugger reset circuit generates a PC87591x reset by a debugger command. This is in addition to the Power-Up}
and Hardware reset sources.
● _{Flash access (control, status, read, write and erase) interface and control is provided. The Debugger interface gen-}
erates a reset signal when JTAG access to the flash is enabled.
4.19.3 Debugger Interface Functional Description
The Debugger interface supports four operating modes: Rx session, Tx session, chip RESET and ABORT. Some of these
modes can be active simultaneously for the same or different processors. The ISE interrupt control block includes hooks to
control these conditions.
Rx Session (Sending Data Downstream)
A message sent downstream by the debugger to a processor is called an Rx session. In an Rx session, a debugger uses
both the TAP and the JTAG to monitor the “busy” indication for the Rx data link. Following a “not busy” indication, a message
is sent to a processor via the JTAG, TAP and Rx data link.
One of the internal ISE interrupts is asserted (if not active) according to the PID field of the instruction currently loaded into
the TAP IR register. The signaled processor accesses the data link via the peripheral bus, reads the message length (op-
tional) and fetches it from the Rx data buffer.
At the end of the data transfer, the processor turns off the “busy” indication of the Rx data link.
Tx Session (Sending Data Upstream)
A message sent upstream by a processor to the debugger is called a Tx session. In a Tx session, one of the processors
tries to own the Tx data link by accessing the Tx semaphore DBGTXLOC register. If successful, it writes a message body
to the Tx data buffer and a message length, in words, to DBGTXST register.
After completion of the data buffer update, the processor sets ASSERT bit in DBGTINT register to 1. This signals the de-
bugger with an active-low pulse on TINT. The debugger reads the data using both the TAP and the JTAG.
At the end of the data transfer, the semaphore circuit is set to “not busy” and TINT is released.
Chip RESET
The PC87591x is reset by a dedicated TAP instruction.
ABORT
Either a TAP instruction or a bit-set operation in DBGABORT register generates an ABORT. Asserting an ISE interrupt to-
gether with a non-zero ABORT_i bit in DBGISESRC register signals an ABORT operation. The ISE interrupt control circuit
asserts the ISE interrupt according to the pre-programed mask bits in ABORT_MASK register. A dedicated circuit, together
with a set of registers in the ISE Interrupt Control, clears the ISE requests after they have been served.
Rx Data Link
The Rx data link consists of an 8-word read/write data buffer, DBGRXD0 to DBGRXD7 registers and the Status (DBGRXST)
register.
On PC87591x reset, DBGRXST register is set to its reset value. On TAP reset, the data link maintains its values.
When the TAP controller is in Update-DR state and the current IR is SCAN_RX, DBGRXDX registers are updated from the
TAP Data Shift (DBGDATA) register. Data is valid to the processor only while BUSY bit in DBGRXST register is set. In this
case (i.e., Update-DR of SCAN_RX), the TAP controller copies the PID and length fields from its IR to the Status register
and sets BUSY bit to 1 in this state.
A processor may turn off the BUSY bit by writing 1 to it. BUSY can be cleared even when TCK is not toggling. The Rx data
link functions in Active or Idle modes.
DBGDATA length is set to the length field of the SCAN_RX instruction before Capture_DR state (see Section 4.19.7 on
page 260). No parallel load is executed in Capture-DR state.
Revision 1.07
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