MC6800 Datasheet, PDF (9/32 Pages) Motorola, Inc – 8-BIT MICROPROCESSING UNIT (MPU)

The HALT line must be in the high state for interrupts to
time PW@H without destroying data within the M PU. TSC
be serviced. Interrupts will be latched internally while HALT
then can be used in a short Direct Memory Access (DMA)
is low.
application.
The ~ has a high-impedance puilup device internal to
Figure 12 shows the effect of TSC on the MPU. TSC must
the chip; however, a 3 kQ external resistor to VCC should be
have its transitions at tTSE (three-state enable) while holding
used for wire-OR and optimum control of interrupts.
+1 high and +2 low as shown, The Address Bus and Rl~
line will reach the high-impedance state at tTSD (three-state
Non-Maskable Interrupt (NMI) and Wait for Interrupt
delay), with VMA being forced low. In this exampl$~%the
(WAI) – The MCWCO is capable of handling two types of in-
Data Bus is also in the high-impedance state while,,~;~@&-
terrupts: maskable (~) as described earlier, and non-
ing held low since DBE= 42. At this point in ti@e~,$,’)~MA
maskable (~) which is an edge sensitive input. IRQ is
transfer could occur on cycles #3 and #4. -+$~SC
is
maskable by the interrupt mask in the condition code register
returned low, the MPU Address and R/~lfl&/&Mrn
to the
while ~ is not maskable. The handling of these interrupts
bus. Because it is too late in cycle #5 to,,~cp~,~emory, this
by the M PU is the same except that each has its own vector
address. The behavior of the MPU when interrupted is
shown in Figure 9 which details the MPU response to an in-
terruDt while the MPU is executina the control ~roaram. The
cycle is dead and used for synchroni$~~w.i$~rogram
tion resumes in cycle #6.
‘1~~$..’*~’.\:k~:.:\~!.,~3.::,~l..’>;.
execu-
Valid Memory Address (VM&,~~$ This output indicates to
interrupt shown could be either ~Q or ~ and ca~ be asyn-
peripheral devices that the~@&.@~a~?daddress on the address
chronous with respect to +2. The interrupt is shown going
bus. In normal operation~<gti~, signal should be utilized for
low at time tpcs in cycle #1 which precedes the first cycle of
an instruction (OP code fetch). This instruction is not ex-
enabling peripheral i.~yt;f.~%f~,,wa:’.~~+~sbuch as the PIA and ACiA.
This signal is not thr@T~te. One standard TTL load and
ecuted but instead the Program Counter (PC), Index
Register (IX), Accumulators (ACCX), and the Condition
90 pF may be d~&ly dfiven by this active high signal.
~.,,,+$.:s>:
..?X>L’?.~*~’.
Code Register (CCR) are pushed onto the stack,
HALT - ~h”~$’~%is level sensitive input is in the low state,
The Interrupt Mask bit is set to prevent further interrupts.
The address of the interrupt service routine is then fetched
all activik-.~:<~~.o.~?~~~e machine will be halted. This input is level
sensitj,ve. +i.,,
fram FFFC. FFFD for an NMI interruDt and from FFF8, FFF9
l.ti~~
line provides an input to the MPU to allow con-
for an ~’interrupt.
Upon complet~on of the interrupt ser-
vice routine, the execution of RTI will pull the PC, IX, ACCX,
and CCR off the stack; the Interrupt Mask bit is restored to
its condition prior to Interrupts (see Figure 10).
{W,gf”Program execution by an outside source. If HALT is
+..~.g@ the MPU will execute the instructions; if it is low, the
‘~+,“’t*v~:Pa,U:: ^{will go to a halted or idle mode. A response signal, Bus}
“’t~, Available (BA) provides an indication of the current MPU
Figure 11 is a similar interrupt sequence, except in this _$’+ status. When BA is low, the MPU is in the process of ex-
case, a WAIT instruction has been executed in prepara$$~
ecuting the control program; if BA is high, the MPU has
for the interrupt. This technique speeds up the M&U’”~
halted and all internal activity has stopped,
response to the interrupt because the stacking of tbe~~~$.W,
When BA is high, the Address Bus, Data Bus, and Rl~
ACCX, and the CCR is already done. While t~~$fM@ iS
line will be in a high-impedance state, effectively removing
waiting for the interrupt, Bus Available wilP&@+{Q?~h in-
the MPU from the system bus. VMA is forced low so that the
dicating the following states of the control lj~~Y~MA is low,
floating system bus will not activate any device on the bus
and the Address Bus, R/~and Data B~~ ~~, ~{ in the high
that is enabled by VMA.
impedance state. After
previously described.
the interrupt
w,}.,\i-,t$?*~,,.,<::
IS serviced as
While the MPU is halted, all program activity is stopped,
and if either an ~ or IRQ interrupt occurs, it will be latched
A 3-10 kQ external resistor to V&*’&~&tild be used for wire-
into the MPU and acted on as soon as the MPU is taken out
OR and optimum control of _{,.*.i.$+g.,,i.~r“~$w,’~t~.}
MEMORY MAP.@R IMRRUPT VECTORS
of the halted mode. If a RESET command occurs while the
MPU is halted, the following states occur: VMA= low,
BA= low, Data Bus= high impedance, Rl~= high (read
~:.$ _{‘*, ,,$’}
Vetior ,.., ;. ‘~’
MS
,,f*y
Description
state), and the Address Bus will contain address FFFE as
long as RESET is low, As soon as the RESET line goes high,
the MPU will go to locations FFFE and FFFF for the address
FFFE :,* E=3
FFFQ”J” %FFD
Reset
Non-Maskable Interrupt
of the reset routine.
Figure 13 shows the timing relationships involved when
E&.~\x}i,$ FFFB
Software Interrupt
halting the MPU. The instruction illustrated is a one byte, 2
‘$,~aip” ~
— Interrupt Request
cycle instruction such as CLRA. When HALT goes low, the
MPU will halt after completing execution of the current in-
struction. The transition of HALT must occur tpcs before
Three-State Control (TSC) – When the level sensitive
Three-State Control (TSC) line is a logic “l”, the Address
Bus and the Rim line are placed in a high-impedance state.
VMA and BA are forced low when TSC= “1” to prevent
false reads or writes on any device enabled by VMA. It is
necessary to delay program execution while TSC is held
high. This is done by insuring that no transitions of 41 (or 42)
occur during this period. (Logic levels of the clacks are irrele-
vant so long as they do not change). Since the MPU is a
dynamic device, the 01 clock can be stopped for a maximum
the trailing edge of @l of the last cycle of an instruction
(point A of Figure 13). HALT must not go low any time later
than the minmum tpcs specified.
The fetch of the OP code by the M PU is the first cycle of
the instruction. If HALT had not been low at Point A but
went low during 42 of that cycle, the MPU would have
halted after completion of the following instruction. BA will
go high by time tBA (bus available delay time) after the last
instruction cycle. At this point in time, VMA is low and R/~,
Address Bus, and the Data Bus are in the high-impedance
state.
MOTOROLA
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Semiconductor Products Inc.
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