MC6800 Datasheet, PDF (7/32 Pages) Motorola, Inc – 8-BIT MICROPROCESSING UNIT (MPU)

MPU SIGNAL DESCRIPTION
Proper operation of the MPU requires that certain control
Read (high) or Wrile (low) state, The normal standby state of
and timing signals be provided to accomplish specific func-
this signal is Read (high). Three-State Control going high will
tions and that other signal lines be monitored to determine
turn Read/Write to the off (high impedance) state. Also,
the state of the processor.
when the processor is halted, it will be in the off state. This
output is capable of drivina one standard TTL Ioa&?iqnd
Clocks Phase One and Phase Two (o1, 42) – Two pins
90 pF.
are used for a two-phase non-overlapping clock that runs at
~+,r+i~ .:}
the VCC voltage level.
RESET – The RESET input is used to rese~&}N~&~rt the
Figure 1 shows the microprocessor clocks. The high level
M PU from a power down condition resulti~~,jf~% a power
is specified at VIHC and the low level is specified at VILC.
The allowable clock frequency is specified by f (frequency).
The minimum @l and @2 high level pulse widths are specified
by PW~H (pulse width high time). To guarantee the required
failure or initial start-up of the processor,+:~@l%~i&el sensitive
input can also be used to reinitialize t,$~~~~~ne at any time
after start-up.
.)’ k%}?*
:t:;l,\ \
If a high level is detected in th~ Inpw; this will signal the
access time for the peripherals, the clock up time, tut, is
MPU to begin the reset seqe~$~. During the reset se-
specified. Clock separation, td, is measured at a maximum
quence, the contents of th,~?%f$wb locations (FFFE, FFFF)
voltage of VOV (overlap voltage), This allows for a multitude
in memory will be loade@{~~&,Jtie Program Counter to point
of clock variations at the system frequency rate.
to the beginning of.~.,.$\~J~tb.~.:,w,~eyt.. routine. During the reset
routine, the interrupt ~s~ bit is set and must be cleared
under program c~~ol, before the M PU can be interrupted by
Address Bus (AOA15) – Sixteen pins are used for the ad-
IRQ. While ‘K%Jk’’low
(assuminga minimum of8 clock
dress bus. The outputs are three-state bus drivers capable of
cycles have ~Jcc~$r8d) the MPU output signals will be in the
driving one standard TTL load and 90 pF. When the output is
followinqj$&MVMA=
low, BA= low, Data Bus= high im-
turned off, it is essentially an open circuit. This permits the
peda~~e,>~~~= high (read state), and the Address Bus will
MPU to be used in DMA applications. Putting TSC in its high
state forces the Address bus to go into the three-state mode.
Data Bus (DO-D7) – Eight pins are used for the data bus.
con$&8?}4the ‘reset address FFFE. Figure 8 illustrates a power
&“~q@~nce using the RESET control line. After the power
~i. _{~,P@ reaches 4.75 V, a minimum of eight clock cycles are}
?$:jlj$~qtiired for the processor to stabilize in preparation for
It is bidirectional, transferring data to and from the memory
‘~trestarting. During these eight cycles, VMA will be in an in-
and peripheral devices. It also has three-state output buffer$
.lp~ determinate state so any devices that are enabled by VMA
capable of driving one standard TTL load and 130 pF. D,a~$,
which could accept a false write during this time (such as
Bus is placed in the three-state mode when DBE is Io#t\,t w~$.
,{’.y.,.,.:!>:.?:>..
.+,‘.+:+‘ ‘”$,. ?
battery-backed RAM) must be disabled until VMA is forced
low after eight cycles. RESET can go high asynchronously
Data Bus Enable (DBE) – This level sensitive i~[~t~$sthe
with the system clock any time after the eighth cycle.
three-state control signal for the M PU data ~$~l:~yd will
enable the bus drivers when in the high st~:&$$@j9 Input is
RESET timing is shown in Figure 8. The maximum rise and
TTL compatible; however in normal op~,atib~~$twould
be
fall transition times are specified by tpcr and tpcf. If RESET
driven by the phase two clock. Durin&@n~~,K~ read cycle,
is high at tpcs (processor control setup time), as shown in
the data bus drivers will be disabled,’~~t~nal ly. When it is
Figure 8, in any given cycle then the restart sequence will
desired that another device contr$PtR~&ata bus, such as in
begin on the next cycle as shown. The RESET control line
Direct Memory Access (DMA)j+~k~@~ions,
held low.
.>.:,:,.,~,x.t~
DBE should be
may also be used to reinitialize the MPU system at any time
during its operation. This is accomplished by pulsing RESET
If additional data setup+p[+ho~d~?me is required on an MPU
low for the duration of a minimum of three complete 42
write, the DB E down ,~,~~ @n be decreased, as shown in
cycles. The RESET pulse can be completely asynchronous
Figure 3 (DBE#@2\R:~~e~inimum
down time for DBE is
with the MPU system clock and will be recognized during 42
tDB E as shown, ~~~.s}~ting
D B E with respect to E, data
if setup time tpcs is met.
setup or hold t~,$@#
;>L:.,.\?\\~J$,.
be increased.
Interrupt Request (~Q) – This level sensitive input re-
Bus Ay~i$~l~.(bA) – The Bus Available signal will nor-
quests that an interrupt sequence be generated within the
mally ~%..,~*.’:* ~Y}$’low state; when activated, it will go to the
high.?ata~:+indicating
that the microprocessor has stopped
and ^{*@“’,“@’*’tl+fhe} address bus is available. This will occur if the
machine. The processor will wait until it completes the cur-
rent instruction that is being executed before it recognizes
the request. At that time, if the interrupt mask bit in the Con-
HALT~ne is in the low state or the processor is in the WAIT
dition Code Register is not set, the machine will begin an in-
state as a result of the execution of a WAIT instruction. At
terrupt sequence. The Index Register, Program Counter, Ac-
such time, all three-state output drivers will go to their off
cumulators, and Condition Code Register are stored away on
state and other outputs to their normally inactive level. The
the stack. Next, the MPU will respond to the interrupt re-
processor is removed from the WAIT state by the occurrence
quest by setting the interrupt mask bit high so that no further
of a maskable (mask bit I = O) or nonmaskable interrupt, This
interrupts may occur. At the end of the cycle, a 16-bit ad-
output is capable of driving one standard TTL load and
dress will be loaded that points to a vectoring address which
30 pF. If TSC is in the high state, Bus Available will be low,
is located in memory locations FFF8 and FFF9. An address
loaded at these locations causes the MPU to branch to an in-
Read/Write (R/~) – This TTL compatible output signals
terrupt routine in memory. Interrupt timing is shown in
the peripherals and memory devices wether the MPU is in a
Figure 9.
MOTOROLA
@
Semiconductor Products Inc.
7