MC6800 Datasheet, PDF (21/32 Pages) Motorola, Inc – 8-BIT MICROPROCESSING UNIT (MPU)

FIGURE 24 – CONDITIONAL BRANCH INSTRUCTIONS
BMI :
BPL :
N=l
;
N=@ ;
BEQ :
BNE :
Z=l
;
Z=4 ;
BVC :
BVS :
V=$
;
V=l
;
BCC :
BCS :
C=$ ;
C=l
;
BHI :
BLS :
c+ z=@ ;
C+z=l
;
BLT :
BGE :
N@V=l
;
N@ V=@ ;
BLE :
Z+(N@V)=l
BGT :
Z+(N@V)=@
;
The conditional branch instructions, Figure 24, consists of
seven pairs of complementary instructions. They are used to
test the results of the preceding operation and either con-
tinue with the next instruction in sequence (test fails) or
cause a branch to another point in the program (test suc-
ceeds).
Four of the pairs are used for simple tests of status bits N,
Z, V, and C:
1. Branch on Minus (B MI) and Branch On Plus (BPL) tests
the sign bit, N, to determine if the previous result was
negative or positive, respectively.
2. Branch On Equal (BEQ) and Branch On Not Equal
(BNE) are used to test the zero status bit, Z, to determine
whether or not the result of the previous operation was equal
to zero. These two instructions are useful following a Com-
pare (CMP) instruction to test for equality between an ac-
cumulator and the operand. They are also used following the
Bit Test (BIT) to determine whether or not the same bit pos~~
tions are set in an accumulator and the operand.
,Y>.)...t.;,..~’,:,
3. Branch On Overflow Clear (BVC) and Branc@$~ns
Overflow Set ( BVS) tests the state of the V bit to ~&~*e
if the previous operation caused an arithmetic Q@r,@~
4. Branch On Carry Clear (BCC) and Branch @~b$rY
Set
( BCS) tests the state of the C bit to determ~~$$~~~previous
operation caused a carry to occur. BCC ~~,~~~b are useful
.,*.J?,’-~>‘,:?
for testing relative magnitude when the values being tested
are regarded as unsigned binary numbers, that is, the values
are in the range 00 (lowest) to FF (highest). BCC following a
comparison (CMP) will cause a branch if the (unsigned)
value in the accumulator is higher than or the same as the
value of the operand. Conversely, BCS will cause a branch if
the accumulator value is lower than the operand.
The fifth complementary pair, Branch On Higher (Qi&~~~,nd
Branch On Lower or Same (BLS) are, in a se~~~/~@~-
plements to BCC and BCS. BHI tests for both C ~n@~~O; if
used following a CMP, it will cause a branc~,?k~~pWalue in
the accumulator is higher than the oper&~~%50nversely,
BLS will cause a branch if the unsignq~’~~a~’”value
in the
accumulator is lower than or the saW:~$J&b operand.
The remaining two pairs are u~~l ~ ‘testing results of
operations in which the values at% re&~Yded as signed two’s
complement numbers. This $%&&}{rom the unsigned binary
case in the following sen:~+~~.{~nsigned, the orientation is
higher or lower; in si~w’~,wo’s
complement, the com-
parison is between @$~~g~&~ smaller where the range of
values is between – 1~,.,and + 127.
Branch On L@$~$anZero
(BLT) and Branch On Greater
Than Or Eq~#k.~~~’~~G E) test the status bits for N @V= 1
and N e V{~$<,,r~pectively.
B LT will always cause a branch
followin$~~s 8~~ration in which two negative numbers were
adde,~. in’~dition, it will cause a branch following a CMP in
wh#~$Jhe value in the accumulator was negative and the
,@$&~~n’&was positive. B LT will never cause a branch follow-
.,:t~@,$#CMP in which the accumulator value was positive and
{,f,$+:,,,...j::w} _{e operand negative. BGE, the complement to BLT, will}
‘*N cause. a branch following operations in which two positive
,+::> _{values were added or in which the result was zero.}
The last pair, Branch On Less Than Or Equal Zero (BLE)
and Branch On Greater Than Zero (BGT) test the status bits
for Z@ (N+V) = 1 and Z@ (N +V) =0, respectively. The ac-
tion of BLE is identical to that for BLT except that a branch
will also occur if the result of the previous result was zero,
Conversely, BGT is similar to BGE except that no branch will
occur following a zero result.
‘ i$,:;,;i*
,,,1.,.
..
. .^.,.y?“s^~$.,~, $$:’
‘$?l.~,,~k,J.F
CONDITION CODE REGISTER
OPERATIONS
The Condition ~~~~Register
(CCR) is a 6-bit register
to precede any SEI instruction with an odd opcode – such
within the MPU~~~kl$*useful
in controlling program flow
as NOP. These precautions are not necessary for MC~
during system d;%tlon.
The bits are defined in Figure 25.
processors indicating manufacture in November 1977 or
The instr~~lia~% shown in Table 5 are available to the user
later.
for dire~#~@@@ulation of the CCR.
Systems which require an interrupt window to be opened
A C~,$A/ instruction sequence operated properly, with
under program control should use a CLI-NOP-SEI sequence
earl~:~~$~~
processors, only if the preceding instruction
rather than CLI-SEI.
was $~d (Least Significant Bit= 1), Similarly it was advisable
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