MC6800 Datasheet, PDF (15/32 Pages) Motorola, Inc – 8-BIT MICROPROCESSING UNIT (MPU)

PROGRAM CONTROL OPERATIONS
Program Control operation can be subdivided into two
categories: (1) Index Register/ Stack Pointer instructions; (2)
Jump and Branch operations.
Index Register/ Stack Pointer Operations
The instructions for direct operation on the MPU’S Index
Register and Stack Pointer are summarized in Table 3.
Decrement (DEX, DES), increment (INX, INS), load (LDX,
LDS), and store (STX, STS) instructions are provided for
both. The Compare instruction, CPX, can be used to com-
pare the Index Register to a 16-bit value and update the Con-
dition Code Register accordingly.
The TSX instruction causes the Index Register to be load-
ed with the address of the last data byte put onto the
“stack. ” The TXS instruction loads the Stack Pointer with a
value equal to one less than the current contents of the Index
Register. This causes the next byte to be pulled from the
“stack” to come from the location indicated by the index
Register. The utility of these two instructions can be clarified
by describing the “stack” concept relative to the M@W
system.
The “stack” can be thought of as a sequential list of data
stored in the MPU’S read/write memory. The Stack Pointer
contains a 16-bit memory address that is used to access the
list from one end on a last-in-first-out (LIFO) basis in contrast
to the random access mode used by the MPU’S other ad-
dressing modes.
The MC~ instruction set and interrupt structure allow
extensive use of the stack concept for efficient handling of
data movement, subroutines and interrupts. The instructi~.os
can be used to establish one or more “stacks” anywhg~~~<
read/write memory. Stack length is limited only <,q~$~~e
amount of memory that is made available.
.,is,~ _,.,
Operation of the Stack Pointer with the Pus@,@i~~,Rtillin-
structions is illustrated in Figures 15 and 1~~..%~.$ush in-
struction (PS HA) causes the contents of kd$~~icated ac-
cumulator (A in this example) to be stor~+in;wemory at the
location indicated by the Stack Point@r. ~Q&Stack Pointer is
automatically decremented by ~~~~$~t~wing the storage
operation and is “pointing” to th~~:~e{$empty stack location.
The Pull instruction (PULA ..@~:~%’B) causes the last byte
stacked to be loaded intothe:w’ropriate
accumulator. The
Stack Pointer is automatically incremented by one just prior
to the data transfer so that it will point to the last byte stack-
ed rather than the next empty location. Note that the PULL
instruction does not “remove” the data from memory; in the
example, 1A is still in location (m+ 1) following execution of
PULA. A subsequent PUSH instruction would overw~jt~~at
location with the new “pushed” data.
‘..$.,,*,,..$,,.:
i:~).:~~.f.,k\,
Execution of the Branch to Subroutine (B SR)a$d. #~rrfp to
Subroutine (JSR) instructions cause a returD%~*~ to be
saved on the stack as shown in Figures 18$~w~@ 20. The
stack is decremented after each byte of,.#$r@?n address is
pushed onto the stack. For both of$&~~N@structions, the
return address is the memory locatid~ f~jo’wing the bytes of
code that correspond to the B,S$.:an’~:$&SRinstruction. The
code required for BSR or J g~g”~<y be either two or three
bytes, depending on whet~r,%~.J S R is in the indexed (two
bytes) or the extende~$~$~$@ bytes) addressing mode.
Before it is stacked, t@<&~$Yam Counter is automatically in-
cremented the correct Rgmber of times to be pointing at the
location of the ~$~~~$truction. The Return from Subroutine
lnstruction,,,@K$~~puses the return address to be retrieved
and Ioade@ I$to t~e Program Counter as shown in Figure 21.
There $r~s~$eral operations that cause the status of the
M PU.,$0b$wved on the stack. The Software Interrupt (SWI)
and$%ait for Interrupt (WAI) instructions as well as the
~?~,ah~e (~Q) and non-maskable (N MI) hardware inter-
-$ ‘~~@J&all cause the M PU’S internal registers (except for the
*,.,,.,.,~:f,?@tack Pointer itself) to be stacked as shown in Figure 23.
,,\.“$k
MPU status is restored
shown in Figure 22.
by the Return
from
Interrupt,
RTI, as
Jump and Branch Operation
The Jump and Branch instructions are summarized in
Table 4. These instructions are used to control the transferor
operation from one point to another in the control program.
The No Operation instruction, NOP, while included here,
is a jump operation in a very limited sense. Its only effect is to
increment the Program Counter by one. It is useful during
program development as a “stand-in” for some other in-
struction that is to be determined during debug. It is also us-
ed for equalizing the execution time through alternate paths
in a control program.
I
!*,.
.s. .
, ‘:.
?::r~~~,,,*t>, ~i
.t‘*:Z
?..*
!$s.
PO 1NT$&Q$~&&?10
NS MNEMONIC
Co mp%~$~:her Reg
CPX
o~eq~,:~$ndex
Reg
Oe~.~efit Stack Pntr
lnc;&ment Index Reg
Increment Stack Pntr
Load Index Reg
Load Stack Pntr
Store Index Reg
Store Stack Pntr
Indx Reg +Stack Pntr
Stack Pntr * Indx Reg
OEX
O ES
INX
INS
LOX
LOS
STX
STS
TXS
TSX
iMMED
DIRECT
OP -
8C 3
= OP -
3 9C 4
~ OP
—
2 AC 62
f (TNO
OP
Bc
CE 3
8E 3
3 OE 4
3 9E 4
DF 5
9F 5
2
2
2
2
EE
AE
EF
AF
1⁶²
FE 5
62
BE 5
72
FF 6
72
BF 6
@ (Bit N) Test: Sign bit of most significant
(MS) byte of result=
1?
@ (Bit V) Test: 2s complement
o“erfiow
from subtraction
of m. byte.?
@ (Bit N) Test: Result Iesstha”
zero? (Bit 15= 1)
—^IMPL—^IEO
OP
—
—
09 4
34 4
08 4
31 4
35 4
—30 —4
I
BOOLEAN/ARITHMETIC
OPERATION
~
1
1
1
1
I
L¹
1
X–l+x
SP–1-SP
X+l+x
SP+l+SP
MA XH, (M+l) -XL
M+ SPH, (M+1)4SPL
XH+M,
XL+(M+l)
SPH+M, SPL~(M+l)
X-1-SP
SP+l+X
CO ND. COOEREG
MOTOROLA
@
Semiconductor Products Inc. —
15