MC6800 Datasheet, PDF (25/32 Pages) Motorola, Inc – 8-BIT MICROPROCESSING UNIT (MPU)

Relative Address Mode – In both the Direct and Extended
the unconditional jump (JMP), jump to subroutine (JSR),
nodes, the address obtained by the MPU is an absolute
and return from subroutine (RTS) are used.
~umerical address. The Relative addressing mode, im-
In Figure 32, when the MPU encounters the opcode for
)Iemented for the MPU’S branch instructions, specifies a
BEQ (Branch if result of last instruction was zero), it tests the
nemory location relative to the Program Counter’s current
Zero bit in the Condition Code Register. If that bit is “O,” in-
Dcation. Branch instructions generate two bytes of machine
dicating a non-zero result, the MPU continues execution
:ode, one for the instruction opcode and one for the
with the next instruction (in location WIO in Figure 32). If the
‘relative” address (see Figure 32). Since it is desirable to be
previous result was zero, the branch condition is satisfied
ible to branch in either direction, the 8-bit address byte is in-
and the MPU adds the offset, 15 in this case, to PC+ 2 and
erpreted as a signed 7-bit value; the 8th bit of the operand is
branches to location W25 for the next instruction.
rested as a sign bit, “O”= plus and “1”= minus. The re-
The branch instructions allow the programmer to efficient-
naining seven bits represent the numerical value. This
Iy direct the MPU to one point or another in the contro$.:~ro-
esults in a relative addressing range of * 127 with respect to
gram depending on the outcome of test results. ~W~%e
he location of the branch instruction itself, However, the
control program is normally in read-only memory #ti~$@not
)ranch range is computed with respect to the next instruc-
be changed, the relative address used in execu@~~@t&ranch
ion that would be executed if the branch conditions are not
instructions is a constant numerical valuq~’~~~@-by-cycle
iatisfied. Since two bytes are generated, the next instruction
s located at PC + 2. If D is defined as the address of the
)ranch destination, the range is then:
operation is shown in Table 10 for relat.i}g:\&A,#‘a~Q@ssing.
~\, .!--s!,l.!,,,.,,i,
Indexed Addressing Mode – ~~~~d~xed addressing,
(PC+2)– 127SD S(PC+2)+127
)r
PC–125<D~PC+129
hat is, the destination of the branch instruction must be
vithin – 125 to + 1.29 memory locations of the branch in-
the numerical address is variable qnd d~ends on the current
contents of the Index Regis,t.e‘.r~~@*’,.\..+\-\~.,::.~)~Y!f‘.J$‘>\~,o.urce statement such as
Operator Operan~*~~~ ~ Comment
STAA
X Ut;;:~@&T A IN INDEXED LOCATION
*\+~*%\.g: ;~
truction itself. For transferring control beyond this range,
causes the M PU,:~q.,)stalk the contents of accumulator A in
.,.t$J;:..,?~;<,\{y..,\\
TABLE 6 – INHERENT MODE CYCLE-BY-CYCLE~~~~*lON
Addre* Mode
and I nmructions
ABA
ASL
ASR
CBA
CLC
CLI
CLR
CLV
COM
DES
DEX
INS
INX
DAA
DEC
INC
LSR
NEG
NOP
ROL
ROR
SBA
SEC
SE I
SEV
TAB
TAP
TBA
TPA
TST
Cycles
2
4
Cycle
#
1
2
1
2
3
4
VMA
Lina
1
1
1
,,+?
,:~, ,@ ~~’lw
Address Bus
,% ^{~t..r:].i:,~’ Lina}
...,-.,<,,,;,,
Op Code Address
.c,:,..~~t*,,,:,r,.,, ^.l’:.+
1
~.i: .$.
OP Code Addrass + 1 ~*.st,&$f~
1
‘!><::+:$<>
~,.;*:~\,
.,?-
.fi ^>~:k(.’
~~~,
:$,.~>~, ^~i,\~.,,,,.\
..*Y-. “’?.
0 p$**j$dHress
1
1
~~.~~$$e Address+ I
1
0 *$~~$~~us Register Contents
1
~..~<f;~~~~w Register Contents
1
Data Bus
Op Code
Op Code of Next Instruction
Op Code
Op Code of Next Instruction
Irrelevant Data (Note 1 )
Irrelevant Data (Note 1 )
PSH
1 ,/ S* ‘$~~~?.$OP Code Address
1
Op Code
4
.,t~,.:! ,),,,$
g 3 ‘$$,“’” ,
PUL
>~,.,q ^{~p.~ # o}
.?,.4>,~,j$ _,
,
,{.,.-:,~\\, ^{., .}
..+:!~@*” ~}
‘\~\ \\t\*.’
.3..,,, ,.
~:’,$.,$j$“:t
,... “’i:.* .
TSX
‘-?;*-{.-J,Y$.~:.~. .~ik~b.$,,
,.*T. “‘,?.. ‘
.. . . ^{$‘k~~”:+..}:..,.$t“~J$~}
4
*$,f..‘:%”
..,, ^{\***,.Y,~..,’~kq~,,.’}
2
‘
3
0
4
1
1
1
2
1
3
Q
4
0
TX$~~~W ““
y;.
1
1
4
2
1
3
0
4
0
Op Code Addrass + 1
Stack Pointer
Stack Pointer – 1
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
Op Code Address
Op Code Address+ 1
Stack Pointer
New Index Register
Op Code Address
OP Code Address+ 1
Index Register
New Stack Pointer
1
Op Code of Next Instruction
o
Accumulator Data
1
Accumulator Data
1
Op Code
1
Op Code of Next instruction
1
Irrelevant Data (Note 1 )
1
Operand Data from Stack
1
Op Code
1
Op Code of Next Instruction
1
Irrelevant Data (Note 1 )
1
Irrelevant Data (Note 1 )
1
Op Code
1
Op Code of Next Instruction
1
Irrelevant Data
1
Irrelevant Data
RTS
1
1
OP Code Address
1
Op Code
2
1
OP Code Address+ 1
1
Irrelevant Data (Note 2)
5
3
0
Stack Pointer
1
Irrelevant Data (Note 1 )
4
1
Stack Pointer + 1
1
Address of Next Instruction (High
Order Byte)
5
1
Stack Pointer + 2
1
Address of Next Instruction (Low
Order Byte)
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