MC6800 Datasheet, PDF (10/32 Pages) Motorola, Inc – 8-BIT MICROPROCESSING UNIT (MPU)

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To debug programs it is advantageous to step through
programs instruction byinstruction .To do this, HALT must
be brought high for one MPU cycle and then returned low as
shown at point B of Figure 13. Again, the transitions of
HALT must occur tpcs before the trailing edge of $1. BA
will go low at tBA after the leading edge of the next @l, in-
dicating that the Address Bus, Data Bus, VMA and Rl~
Iinesare back on the bus. Asingle byte, 2 cycle instruction
such as LSRisused forth isexample also. During the first cy-
cle, the instruction Y is fetched from address M+l. BA
returns high at tBA on the last cycle of the instruction in-
dicating the MPU is off the bus. If instruction Y had been
three cycles, the width of the BA low time would have been
increased by one cycle.
FIGURE 10 – MPU FLOWCHART
f
Y
1 +BA
Y
I
3
q
1
0^A
1. Reset is recognized at any position in the flowchart.
2 Instructions which affect the l-Bit act upon a on~bh buffer register,
“lTMP.” This has the effect of delaying any CLEARING of the l-Bit one
clock time. Setting the l-Bit, however, is not delayed.
3 See Tables 6-11 for details of Instruction Execution.
m ^MOTOROLA
Semiconductor Products Inc.
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