MC6800 Datasheet, PDF (17/32 Pages) Motorola, Inc – 8-BIT MICROPROCESSING UNIT (MPU)

TABLE 4 – JUMP AND BRANCH INSTRUCTIONS
OPERATIONS
Branch Always
Branch If Carry Clear
MNEMONIC
BRA
BCC
—
RE h—l T—
G
# G—
G Y_T
24 4 2
—
i— _—
— —#
L
BRANCH TEST
Branch If Carry Set
B CS
25 4 2
Branch If = Zero
BEO
27 4 2
Branch If > Zero
Branch If >Zero
BGE
2C 4 2
BGT
2E 4 2
Branch If Higher
BHI
22 4 2
Branch If < Zero
Branch If Lower Or Same
BLE
2F 4 2
B LS
23 4 2
Branch If < Zero
B LT
20 4 2
Branch If Minus
Branch If Not Equal Zero
Branch If Overflow Clear
Branch If Ovefilow Set
Branch If Plus
BMI
2B 4 2
BNE
26 4 2
BVC
28 4 z
BVS
29 4 2
BPL
2A 4 2
Branch To Subroutine
BSR
80 8 2
Jump
Jump To Subroutine
JMP
JSR
6E
33
AO
93
No Operation
NOP
I
Return From Interrupt
RTI
I
Return From Subroutine
RTS
I
Softwre Interrupt
Swl
I
Wait for Interrupt%
IAI puts Address Bus, RN, and
WAI
ita Businthet
~
—
‘n
~
m
——
I
low
..?
@
—
(All)
~ (Bit 1)
Load Condition
Code Register from Stack. (See Special Op$@tic
Set when interrupt
occurs. if previously
is required to exit the wait state.
set, a Non-MaSk,:~e’’%?errUPt
.* ^{~+. ‘~}
CONO. COOE REG.
T¹⁰
Vc
Execution of the Jump Instruction, JMP, and Branch
Always, BRA, affects program flow as shown in Figure 17.
When the MPU encounters the Jump (Indexed) instruction,
it adds the offset to the value in the Index Register and %,
the result as the address of the next instruction to~b~;~x~$
ecuted. In the extended addressing mode, the add[e~~~?he
next instruction to be executed is fetched from ,$~$~*~~ca-
tions immediately following the JM P instructl~~~}K~WBranch
Always (BRA) instruction is similar to the J~~?~#~&nded) in-
struction except that the relative addre&Sin&. fiode applies
and the branch is limited to the rang~Wtkm$- 125 or + 127
bytes of the branch instruction _{~i~4$.,‘i~...,},..%\?.%,,$.‘~<~e} opcode for the
BRA instruction requires one les$by~ than J M P (extended)
but takes one more cycle to @?
The effect on program fl~~ f$r the Jump to Subroutine
(JSR) and Branch to Sw#rQu{*$ (BSR) is shown in Figures
18 through 20. Note t~%:$@Program Counter is properly in-
cremented to be$:~~~:n~ at the correct return address
before it is stac~&i,;~~#~ration of the Branch to Subroutine
and Jump to a~w~’tine (extended) instruction is similar ex-
cept for th@~~n~&>The BS R instruction requires less opcode
than J $$&R{%Q~#evsersus 3 bytes) and also executes one cy -
‘+~’$.u. sed as the end of a subroutine to return to the main pro-
~y: _{gram as indicated in Figure 21,}
The effect of executing the Software Interrupt, SWI, and
the Wait for Interrupt, WAI, and their relationship to the
hardware interrupts is shown in Figure 22. SW! causes the
M PU contents to be stacked and then fetches the starting
address of the interrupt routine from the memory locations
that respond to the addresses FFFA and FFFB. Note that as
in the case of the subroutine instructions, the Program
Counter is incremented to point at the correct return address
before being stacked. The Return from Interrupt instruction,
RTI, (Figure 22) is used at the end of an interrupt routine to
restore control to the main program. The SWI instruction is
useful for inserting break points in the control program, that
is, it can be used to stop operation and put the MPU
registers in memory where they can be examined. The WAI
instruction is used to decrease the time required to service a
hardware interrupt; it stacks the MPU contents and then
waits for the interrupt to occur, effectively removing the
stacking time from a hardware interrupt sequence,
FIGURE 17 – PROGRAM FLOW FOR JUMP AND BRANCH INSTRUCTIONS
[X+~K
[ ,,-,
(a) Jump
(n+2)*Klxl
qK = Signed 7-bit value
(b) Branch
m
MOTOROLA
Semiconductor Products Inc.
17