MC6800 Datasheet, PDF (23/32 Pages) Motorola, Inc – 8-BIT MICROPROCESSING UNIT (MPU)

For the instructions that use both Direct and Extended
modes, the Assembler selects the Direct mode if the operand
vaiue is in the range O-255 and Extended otherwise. There
are a number of instructions for which the Extended mode is
valid but the Direct is not. For these instructions, the
Assembler automatically selects the Extended mode even if
the operand is in the O-255 range. The addressing modes are
summarized in Figure 26.
Inherent (Includes “Accumulator Addressing” Mode)
The successive fields in a statement are normally
separated by one or more spaces. An exception to this rule
occurs for instructions that use dual addressing in the
operand field and for instructions that must distinguish re-
tween the two accumulators. In these cases, A and B are
“operands” but the space between them and the operator
may be omitted. This is commonly done, resulting in ap-
parent four character mnemonics for those instructions.
The addition instruction, ADD, provides an example of
dual addressing in the operand field:
Operator Operand
Comment
ADDA
or
MEM12 ADD CONTENTS OF MEM12 TO j&~$:k
~~,~~,.,1?t~;~..$..:,~$
ADDB
MEM12 ADD CONTENTS OF MEM_,,1_,~2_i.;,~%_;i:,\,Q_.Jt#_J&_$C₊~_t’$
The example used earlier for the test instru~&~~?ST,
applies to the accumulators and uses th,$~~~~ohulator
dressing mode” to designate which o$,,x’v-accumulators
is being tested:
.jt.
\,.*~\#<~:~,:\$,;.;:
.\~. ;,
also
ad-
Direct:
Example: SUBB Z
Addr. Rane = O–255
A
(K = One-Bvte Oprnd)
(K = Two-Bvte Oprnd)
(K = One-Bvte Oprnd)
(K = Two-Bvte OPrnd)
n
n+l
n+2
DO Instruction
Z = Oprnd Address
Next Instr.
q
z&
OR
.:,,.
*“r,
J
ntl
ZH = Oprnd Addr-s
n+2
ZL = Oprnd Address
n+3
.
Next Instr.
q
z&
OR
z[
KH = Operand
I
n+2
Next Inst.
OR
n+2
I
KL = Operand
I
n+3
I
Next Instr.
I
Relative:
Example: BNE K
Iⁿ
Instruction
I
(K = Signed 7-Bit Value)
Addr. Range:
q
–125t0
+129
Relative to n.
q
(“+2)’K-
~ If Br”ch Tst False, ~ if Brnch Tst True.
Indexad:
n
Instruction
I
Example: ADDA Z, X
Addr. Range:
O–255 Relative to
Index Register, X
‘+1-
n+2
Next Instr.
I
1
o
q
(Z = a-Bit Unsignad
Value)
x+z&
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