MC6800 Datasheet, PDF (26/32 Pages) Motorola, Inc – 8-BIT MICROPROCESSING UNIT (MPU)

I
Address Mode
and Instructions
TABLE 6 – INHERENT MOOE CYCLE-BY-CYCLE
CVcle VMA
Cycles
# Line
Address Bus
OPERATION (CONTINUED)
R lx
Line
Data Bus
WA I
RTI
1
1 Op Code Address
2
1 Op Code Address + 1
3
1 Stack Pointer
4
1 Stack Pointer – 1
9
5
1 Stack Pointer – 2
6
1 Stack Pointer – 3
7
1 Stack Pointer – 4
8
1 Stack Pointer – 5
9
1 Stack Pointer – 6 (Note 3)
1
1 Op Code Address
2
1 Op Code Address+ 1
3
0 Stack Pointer
4
1 Stack Pointer + 1
10
5
1 Stack Pointer + 2
6
1 Stack Pointer + 3
7
1 Stack Pointer + 4
1 Op Code
1 Op Code of Next Instruction
o Return Address (Low Order Byte)
0 Return Address (High Order Byte) ‘Q,,x,
t:f,s:.,;.:~;*$$
0 Index Register (Low Order By&“.G.*.],.>;;!.;~”{$~
0 Index Register (High Ord:[O &#}$
0 Contents of Accumula~~. ~~p~ “p
.’.,,,.\{.~.>,*r<,+
0 Contents of Accurn,~taYM\%$*\~:. _,
1 Contents of CondF@5~,Segister
1 Op Code
,t,.\.,*i+,.,.:.$.),yp
.a>~+m.,
1 Irrelevant ~ata ~@te 2)
1 lrreleva$$k~~a (Note 1 )
...*;,*~~,<\.,+,‘>..+,.>
1 CoRW~&~ti Cond. Code Register from
.^S\i^*?^.@....^”.3:~,*^,.^,s, ^.
1,4 :#&q$ ^{%ts of Accumulator B from Stack}
.3**: ‘%ntents of Accumulator A from Stack
‘f$ac ~y~e~ Register from Stack (High Order
8
1 Stack Pointer + 5
Index Register from Stack ( Low Order
Byte)
Sw I
9
1 Stack Pointer + 6
,>;:
,,,.?:,*.
10
1 Stack Pointer + 7
,,,.y;,:,~‘\.,*,:,.,
~;? ~...k.
,$ ~!’>i, ,;i)
1
1
.+\ \ ..,,....
Op Code Addresq&+,t~S
,,
2
1 Op Code Address ~{~
Next Instruction Address from Stack
(High Order Byte)
1 Next Instruction Address from Stack
(Low Order Byte)
1 .Op Code
1 Irrelevant Data (Note 1 )
3
1
Stack Poi$ter
,><~.
~;
4
1 Stack ,~in~~ – 1
o Return Address (Low Order BVte)
0 Return Address (High Order Byte)
5
1 Sta*~{h!,t<e,r- _...
–2
12
6
1 :@~ok%~inter – 3
~ ‘..S,:...,N.*TY’
J
1 >j‘$:;t*,# Pointer – 4
,.::/,.,. ,:,~<.,:>,
8 ,,{’!~$$ ;$tack Pointer – 5
,:,,i:\i$?\,
%~i> $1 ‘ Stack Pointer – 6
$:TO ;6:r$o _{Stack Pointer – 7}
o Index Register (Low Order Byte)
0 Index Register (High Order Byte)
0 Contents of Accumulator A
0 Contents of Accumulator B
0 Contents of Cond. Code Register
1 Irrelevant Data (Note 1 )
Note 1.
Note 2.
.>’+):$W,$
,~
:;,*
$:.,}
...,.$%“.,’”.J$:,.“,$*?.,..‘>;’ ¹²
:.+;l,+.:y
1 Vector Address FFFA (Hex)
1 Vector Address FFFB (Hex)
1 Address of Subroutine (High Order
Byte)
1 Address of Subroutine (Low Order
Byte)
t$.~
?
~’ .QA:.$~
If device wh.?~~ls,@dressed during this cycle uses VMA, then the Data Bus will go to the high impedance three-state condition.
Dependi,n,~ 4Q b~ capacitance, data from the previous cycle may be retained on the Data Bus.
Data is,@W~@ bv the MPU,
Note 3. Whil@?~$~,~PU is waiting for the interrupt, Bus Available will go high indicating the following states of the control lines: VMA is
lo~@~ess
BUS, RM, and Data Bus are all in the high impedanca State.
,,:‘w:.”‘~.,~jl,
,,<^~J.*^.:\^~\>^>
,:
‘,$.
,.,.!;.,...:,+ ....,y. .:’>”
~’~i>,;,],*;i~.?J>
.l,*!<.
-
th$w.~ory
location specified by the contents of the Index
location 5006, it looks in the next memory location for the
Re@ter (recall that the label “X” is reserved to designate the
value to be added to X (5 in the example) and calculates the
Index Register). Since there are instructions for manipulating
required address by adding 5 to the present Index Register
X during program execution (LDX, INX, DEC, etc.), the in-
value of 4~. In the operand format, the offset may be
dexed addressing mode provides a dynamic “on the fly” way
represented by a label or a numerical value in the range O-255
to modify program activity.
as in the example. In the earlier example, STAA X, the
The operand field can also contain a numetical value that
operand is equivalent to O, X, that is, the O may be omitted
will be automatically added to X during execution. This for-
when the desired address is equal to X. Table 11 shows the
mat is illustrated in Figure 33.
cycle-by-cycle operation for the Indexed Mode of Address-
When the MPU encounters the LDAB (Indexed) opcode in
ing,
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