MC6800 Datasheet, PDF (13/32 Pages) Motorola, Inc – 8-BIT MICROPROCESSING UNIT (MPU)

MPU INSTRUCTION SET
The MC~ instructions are described in detail in the
MWW Programming Manual. This Section will provide a
brief introduction and discuss their use in developing
MC~ control programs. The MC66W has a set of 72 dif-
ferent executable source instructions. Included are binary
and decimal arithmetic, logical, shift, rotate, load, store,
conditional or unconditional branch, interrupt and stack
manipulation instructions.
Each of the 72 executable instructions of the source
language assembles into 1 to 3 bytes of machine code. The
number of bytes depends on the particular instruction and
on the addressing mode. (The addressing modes which are
available for use with the various executive instructions are
discussed later, )
The coding of the first (or only) byte corresponding to an
executable instruction is sufficient to identify the instruction
and the addressing mode. The hexadecimal equivalents of
the binary codes, which result from the translation of the 72
instructions in all valid modes of addressing, are shown in
Table 1. There are 197 valid machine codes, 59 of the 256
possible codes being unassigned.
When an instruction translates into two or three bytes of
code, the second byte, or the second and third bytes con-
tain(s) an operand, an address, or information from which an
address is obtained during execution.
Microprocessor instructions are often divided into three
general classifications: (1) memory reference, so called
because they operate on specific memory locations; (2)
operating instructions that function without needing a
memory reference; (3) 1/0 instructions for transferring data
between the microprocessor and peripheral devices. $+cl+
In many instances, the M Cm performs the sarn”$*a-
tion on both its internal accumulators and ~#r@rnal
memory locations. In addition, the MC%:,~@terface
adapters (PIA and ACIA) allow the MPU t~$~~~k~peripheral
devices exactly like other memory loca@~$.3@#nce, no 1/0
instructions as such are required. Beca&W‘$q,?~@these features,
other classifications are more sui~@fl~&~~b~introducing the
MC66WS instruction set: (1) ,$cc’%hlator and memory
operations; (2) Program cont~~~t~i~p~e~rations;
Code Register operations, _{~,~,,-~,~,,~~,.,~,\,.,%}
.,t;~,\‘.<*.+.!i\\~${.~‘,’~i~,,,:li
(3) Condition
30
31 NOP
12
TAP
TPA
INX
DEX
3A CLV
3B SEV
3C CLC
?D SEC
3E CLI
3F SEI
10 SBA
11 CBA
12
13
14
15
16 TAB
17 TBA
18
19 DAA
1A
IB ABA
Ic
ID
IE
IF
20 BRA
21
22 BHI
23
24
25
2a
27
2a
29
32 PUL
33 PUL
34 DES
35 TXS
36 PSH
37 PSH
38 .
39 RTS
3A “
3B RTI
3C “
3D .
3E WAI
3F Swl
40 NEG
A
80 SUB
A
IMM co
41
81 CMP
A
IMM cl
42
82 SBC
A
IMM C2
43 COM
A
83
C3
44 LSR
A
84 AND
A
IMM C4
45
85 BIT
A
IMM C5
4a ROR
A
88 LDA
A
IMM ca
47 ASR
A
87
C7
48 ASL
A
8a EOR
A
IMM C8
49 ROL
A
a9
4A DEC
A
8A
40
aB
4C INC
A
ac
4D TST
A
8D
4E
8E
CE LDX
4F CLR
A
8F
CF .
50 NEG
B
90
DO SUB
51
91
01 CMP
52
92
D2 SBC
53 COM
B
93
D3 “
54 LSR
B
QA
DIR D4 AND
55
DIR D5 BIT
5a ROR
B
DIR D6 LDA
57 ASR
B
A
DIR D7 STA
5a ASL
B.
A
DIR Da EOR
59 ROL
A
DIR D9 ADC
5A DEC
A
DIR DA ORA
5B
A
DIR DB ADD
5C INC
DIR DC ‘
5D TST
9D
DD .
5E
9E LDS
DIR DE LDX
5F
REL ao
9F STS
DIR DF STX
IND AO sua
A
IND EO SUB
Al CMP
A
[ND El
CMP
REL
A2 SBC
A
IND E2 SBC
REL
IND A3
E3 .
REk
INO A4 AND
A
IND E4 AND
A5 BIT
A
IND E5 BIT
IND A6 LDA
A
IND Ea LDA
INO A7 STA
A
IND E7 STA
IND A8 EOR
A
IND E8 EOR
IND A9 ADC
A
lND E9 ADC
(ND AA ORA
A
IND EA ORA
ac INC
ao TST
AB
INO AC
IND AD
ADD
CPX
JSR
A
IND EB ADD
IND EC .
IND ED .
aE JMP
IND AE LDS
IND EE LDX
6F CLR
IND AF STS
IND EF STX
70 N EG
EXT BO SUB
A
EXT FO SUB
71 .
B1 CMP
A
EXT F1 CMP
A
72 .
B2 SBC
A
EXT F2 SBC
B
73 COM
EXT B3
F3 .
74 LSR
EX1 B4 AND
A
EXT F4 AND
75 .
B5 BIT
A
EXT F5 BIT
A
7a ROR
EXT Ba LDA
A
EXT F6 LDA
B
77 ASR
EX1 B7 STA
A
EXT F7 STA
78 ASL
EX1 Ba EOR
A
EXT F8 EOR
79 ROL
EX1 B9 ADC
A
EXT F9 ADC
7A DEC
EX1 BA ORA
A
EXT FA ORA
7B .
BB ADD
A
EXT FB ADD
7C INC
EX1 BC CPX
EXT FC “
7D TST
EX1 BD JSR
EXT FD .
7E JMP
EX1 BE LOS
EXT FE LDX
7F CLR
EX1 BF STS
EXT FF STX
IMM
IMM
IMM
B
IMM
IMM
B
OIR
B
DIR
B
DIR
B
DIR
B
DIR
B
DIR
B
DIR
B
DIR
B
DIR
B
DIR
B
DIR
DIR
DIR
B
IND
B
IND
B
IND
B
IND
B
IND
B
IND
B
IND
B
IND
B
IND
B
IND
B
IND
IND
IND
B
EXT
B
EXT
B
EXT
B
EXT
a EXT
B
EXT
B
EXT
B
EXT
B
EXT
B
EXT
a EXT
EXT
EXT
Notes: 1 Addressing Modes:
A=
B
REL
INO
IMM
DIR
Accumulator A
= Accumulator B
= Relative
= Indexed
= Immetiate
= Direc?
2. Unassign4 code indicated by J # * )‘.
m ^MOTOROLA
Semiconductor Products Inc.
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