MC68HC08AZ32 Datasheet, PDF (416/424 Pages) Motorola, Inc – Advance Information

Index
Freescale Semiconductor, Inc.
SPRIE bit (SPI receiver interrupt enable bit) . .
223
SPTE bit (SPI transmitter empty bit) . . . . .227
SPTIE bit (SPI transmitter interrupt enable bit)
225
SPWOM bit (SPI wired-OR mode bit)220, 224
SRSR
computer operating properly reset bit
(COP) . . . . . . . . . . . . . . . . . . . . .90
external reset bit (PIN) . . . . . . . . . . . . . .90
illegal address reset bit (ILAD). . . . . . . .90
illegal opcode reset bit (ILOP) . . . . . . . .90
low-voltage inhibit reset bit (LVI) . . . . . .90
power-on reset bit (POR) . . . . . . . . . . . .89
SSREC
MORA . . . . . . . . . . . . . . . . . . . . . . . . .121
stack pointer . . . . . . . . . . . . . . . . . . . . . . . .35
stack pointer (SP) . . . . . . . . . . . . . . . . . . . .54
stack RAM . . . . . . . . . . . . . . . . . . . . . . .35, 55
start bit. . . . . . . . . . . . . . . . . . . . . . . .136, 169
SCI data . . . . . . . . . . . . . . . . . . . . . . . .183
stop bit. . . . . . . . . . . . . . . . . . . . . . . . . . . .169
SCI data . . . . . . . . . . . . . . . . . . . .178, 182
STOP bit (STOP enable bit) . . . . . . . . . . .148
STOP instruction 87, 112, 129, 146, 148, 153,
179, 218, 281
STOP mode. . . . . . . . . . . . . . . . . . . . . . . .292
entry timing . . . . . . . . . . . . . . . . . . . . . .87
recovery from interrupt break. . . . . . . . .87
stop mode . . . . . . . . .129, 145, 153, 193, 281
recovery time . . . . . . . . . . . . . . . . . . . . .73
SWI instruction . . . . . . . . . . .58, 82, 126, 134
system inegration module (SIM)
STOP mode . . . . . . . . . . . . . . . . . . . . . .86
system integration module (SIM). . . . . .70–90
break flag control register (SBFCR). . . .90
break status register (SBSR) . . . . . . . . .88
exception control . . . . . . . . . . . . . . . . . .80
reset status register (SRSR) . . . . .89, 145
SIM counter . . . . . . . . . . . . . .79, 145–146
WAIT mode . . . . . . . . . . . . . . . . . . . . . .85
T
T8 bit (SCI transmitted bit 8) . . . . . . . . . . . 188
T8 bit (transmitted SCI bit 8) . . . . . . . . . . . 168
TCIE bit (SCI transmission complete interrupt
enable bit) . . . . . . . . . . . . . . . . . . . 185
TE bit (SCI transmitter enable bit). . . . . . . 186
TE bit (transmitter enable bit) . . . . . . . . . . 169
thermal characteristics . . . . . . . . . . . . . . . 379
TIMA counter . . . . . . . . . . . . . . . . . . . . . . 244
timer interface module (TIM) . . . . . . . . . ??–278
channel registers (TCH0H/L–TCH3H/L) . .
278
timer interface module (TIMA)
channel registers (TACH0H/L–TACH3H/L)
254
channel status and control registers
(TASC0–TASC3) . . . . . . . . . . . 250
clock input pin (PTD3/TACLK). . . . . . . 245
counter modulo registers
(TAMODH:TAMODL) . . . . . . . . 249
counter registers (TACNTH/L). . .248–249
prescaler . . . . . . . . . . . . . . . . . . . . . . . 233
status and control register (TASC) . . . 246
timer interface module (TIMB)
channel registers (TBCH0H/L–TBCH3H/L)
278
channel status and control registers
(TBSC0–TBSC1) . . . . . . . . . . . 274
clock input pin (PTD3/TBCLK). . . . . . . 269
clock input pin (PTD4/TBCLK). . . . . . . 259
counter modulo registers (TBMODH/L) . . .
273
counter modulo registers (TBMODH:TB-
MODL) . . . . . . . . . . . . . . . . . . . 273
counter registers (TBCNTH/L). . .272–273
counter registers (TBCNTH:TBCNTL). 272
status and control register (TBSC) . . . . . . .
270–271
timer module characteristics . . . . . . . . . . . 388
TOF bit (TIM overflow flag bit) . . . . . 247, 271
TOIE bit (TIM overflow interrupt enable bit) . .
247, 271
TOVx bits (TIM toggle on overflow bits) . 253,
MC68HC08AZ32
414
Index
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