MC68HC08AZ32 Datasheet, PDF (191/424 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Serial Communications Interface Module (SCI)
I/O registers
FEIE — Receiver framing error interrupt enable bit
This read/write bit enables SCI error CPU interrupt requests
generated by the framing error bit, FE. Reset clears FEIE.
1 = SCI error CPU interrupt requests from FE bit enabled
0 = SCI error CPU interrupt requests from FE bit disabled
PEIE — Receiver parity error interrupt enable bit
This read/write bit enables SCI receiver CPU interrupt requests
generated by the parity error bit, PE. (see SCI status register 1
(SCS1) on page 189). Reset clears PEIE.
1 = SCI error CPU interrupt requests from PE bit enabled
0 = SCI error CPU interrupt requests from PE bit disabled
SCI status register
1 (SCS1)
SCI status register 1 contains flags to signal the following conditions:
• Transfer of SCDR data to transmit shift register complete
• Transmission complete
• Transfer of receive shift register data to SCDR complete
• Receiver input idle
• Receiver overrun
• Noisy data
• Framing error
• Parity error
Bit 7
6
5
4
3
2
SCS1 ^{Read: SCTE}
TC
SCRF IDLE
OR
NF
$0016 _Write:
Reset: 1
1
0
0
0
0
= Unimplemented
Figure 8. SCI status register 1 (SCS1)
1
Bit 0
FE
PE
0
0
27-sci
MOTOROLA
Serial Communications Interface Module (SCI)
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MC68HC08AZ32
189