MC68HC08AZ32 Datasheet, PDF (411/424 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Index
E
EEACR
EEPROM array configuration register . .48
EECR
EEPROM control register. . . . . . . . . . . .46
EENVR
EEPROM non-volatile register . . . . . . . .48
EEPROM. . . . . . . . . . . . . . . . . . . . . . . .40–49
block protection . . . . . . . . . . . . . . . . . . .44
configuration . . . . . . . . . . . . . . . . . . . . .44
EEACR. . . . . . . . . . . . . . . . . . . . . . . . . .48
EECR . . . . . . . . . . . . . . . . . . . . . . . . . . .46
EENVR. . . . . . . . . . . . . . . . . . . . . . . . . .48
erasing . . . . . . . . . . . . . . . . . . . . . . . . . .42
programming . . . . . . . . . . . . . . . . . . . . .41
size. . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
EEPROM control register (EECR1). .392–393
EESEC
MORB . . . . . . . . . . . . . . . . . . . . . . . . .122
electrostatic damage . . . . . . . . . . . . . . . . .308
ELSxA/B bits (TIM edge/level select bits) 252,
276
ENSCI bit (enable SCI bit). . . . . . . . .169, 182
EPROM/OTPROM security . . . . . . . . . . . .120
external crystal . . . . . . . . . . . . . . . . . . . . . .87
external filter capacitor . . . . . . . . . . .102, 115
external filter capacitor pin (CGMXFC) . . .102
external pin reset. . . . . . . . . . . . . . . . . . . . .74
F
f_BUS (bus frequency). . . . . . . . . . . . . . . . . . .99
FE bit (SCI framing error bit) . . . . . . . . . . .178
FE bit (SCI receiver framing error bit) . . . .192
FEIE bit (SCI framing error interrupt enable bit)
178
FEIE bit (SCI receiver framing error interrupt
enable bit). . . . . . . . . . . . . . . . . . . .189
flag protection in break mode . . . . . . . . . . .84
f_NOM (nominal center-of-range frequency) . .96
f_rclk (PLL reference clock frequency) . . . . . .99
f_RCLK (PLL reference clock frequency) . . . . .96
f_RDV (PLL final reference frequency) . . . . . .96
functional operating range. . . . . . . . . . . . .379
f_VCLK (VCO output frequency) . . . . . . . . . . . 96
f_VRS (VCO programmed center-of-range fre-
quency) . . . . . . . . . . . . . . .96, 99, 110
H
H bit
CCR. . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
I
I bit
CCR. . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
I bit (interrupt mask) . . . . . . . . . . . . . 157, 161
I/O port register summary . . . . . . . . . . . . . 308
I/O registers
locations . . . . . . . . . . . . . . . . . . . . . . . . 24
IAB (internal address bus) . . . . . . . . . . . . 124
IBUS . . . . . . . . . . . . . . . . . . . . . . . . . . . 73, 79
IDLE bit (SCI receiver idle bit). . . . . . 178, 190
idle character . . . . . . . . . . . . . . . . . . . . . . 171
ILAD
SRSR. . . . . . . . . . . . . . . . . . . . . . . . . . . 90
ILIE bit (SCI idle line interrupt enable bit) 178,
186
ILOP
SRSR. . . . . . . . . . . . . . . . . . . . . . . . . . . 90
ILOP bit (illegal opcode reset bit) . . . . . . . . 90
ILTY bit (SCI idle line type bit) . . . . . . . . . 183
IMASK1 bit (IRQ interrupt mask bit) . 157, 161
IMASKK
Keyboard interrupt mask bit. . . . . . . . . 304
index register (H:X) . . . . . . . . . . . . . . . . 54, 82
input capture . . . . . . . . . . . . . . .236, 261, 278
interrupt
external interrupt pin (IRQ) . . . . . . . . . . 15
interrupt status and control register (ISCR) . .
156
interrupts
ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
CGM . . . . . . . . . . . . . . . . . . . . . . . . . . 111
msCAN08 . . . . . . . . . . . . . . . . . . . . . . 341
IRQ latch . . . . . . . . . . . . . . . . . . . . . . . . . . 156
IRQ pin . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
IRQ status and control register (ISCR) . . . 160
MOTOROLA
Index
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