MC68HC08AZ32 Datasheet, PDF (300/424 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Analog-to-Digital Converter (ADC)
Table 2. ADC clock divide ratio
ADIV2
0
0
0
0
1
ADIV1 ADIV0 ADC Clock Rate
0
0
ADC input clock /1
0
1
ADC input clock / 2
1
0
ADC input clock / 4
1
1
ADC input clock / 8
X
X
ADC input clock / 16
X = don’t care
ADICLK — ADC input clock select
ADICLK selects either bus clock or cgmxclk as the input clock source
to generate the internal ADC clock. Reset selects cgmxclk as the ADC
clock source.
If the external clock (cgmxclk) is equal or greater than 1MHz, cgmxclk
can be used as the clock source for the ADC. If cgmxclk is less than
1MHz, use the PLL generated bus clock as the clock source. As long
as the internal ADC clock is at approximately 1MHz, correct operation
can be guaranteed. See Conversion time on page 290.
1 = Internal bus clock
0 = External clock (cgmxclk)
NOTE: During the conversion process, changing the ADC clock will result in an
incorrect conversion.
MC68HC08AZ32
298
Analog-to-Digital Converter (ADC)
For More Information On This Product,
Go to: www.freescale.com
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