MC68HC08AZ32 Datasheet, PDF (128/424 Pages) Motorola, Inc – Advance Information

Break Module
Freescale Semiconductor, Inc.
CPU during break
interrupts
The CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD
in monitor mode)
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
TIM and PIT during A break interrupt stops the timer counter.
break interrupts
COP during break The COP is disabled during a break interrupt when V_HI is present on the
interrupts
RST pin.
MC68HC08AZ32
126
Break Module
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Go to: www.freescale.com
4-brk
MOTOROLA