MC68HC08AZ32 Datasheet, PDF (190/424 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Serial Communications Interface Module (SCI)
SCC3
$0015
Read:
Write:
Reset:
Bit 7
6
5
R8
T8
R
4
3
2
1
R
ORIE NEIE FEIE
U
U
0
0
0
0
0
= Unimplemented
U = Unaffected
R = Reserved
Figure 7. SCI control register 3 (SCC3)
Bit 0
PEIE
0
R8 — Received bit 8
When the SCI is receiving 9-bit characters, R8 is the read-only ninth
bit (bit 8) of the received character. R8 is received at the same time
that the SCDR receives the other 8 bits.
When the SCI is receiving 8-bit characters, R8 is a copy of the eighth
bit (bit 7). Reset has no effect on the R8 bit.
T8 — Transmitted bit 8
When the SCI is transmitting 9-bit characters, T8 is the read/write
ninth bit (bit 8) of the transmitted character. T8 is loaded into the
transmit shift register at the same time that the SCDR is loaded into
the transmit shift register. Reset has no effect on the T8 bit.
ORIE — Receiver overrun interrupt enable bit
This read/write bit enables SCI error CPU interrupt requests
generated by the receiver overrun bit, OR.
1 = SCI error CPU interrupt requests from OR bit enabled
0 = SCI error CPU interrupt requests from OR bit disabled
NEIE — Receiver noise error interrupt enable bit
This read/write bit enables SCI error CPU interrupt requests
generated by the noise error bit, NE. Reset clears NEIE.
1 = SCI error CPU interrupt requests from NE bit enabled.
0 = SCI error CPU interrupt requests from NE bit disabled
MC68HC08AZ32
188
Serial Communications Interface Module (SCI)
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