MC68HC08AZ32 Datasheet, PDF (126/424 Pages) Motorola, Inc – Advance Information

Break Module
Freescale Semiconductor, Inc.
Features
Features of the break module include the following:
• Accessible I/O registers during the break interrupt
• CPU-generated break Interrupts
• Software-generated break interrupts
• COP disabling during break interrupts
Functional description
When the internal address bus matches the value written in the break
address registers, the break module issues a breakpoint signal (BKPT)
to the SIM. The SIM then causes the CPU to load the instruction register
with a software interrupt instruction (SWI) after completion of the current
CPU instruction. The program counter vectors to $FFFC and $FFFD
($FEFC and $FEFD in monitor mode).
The following events can cause a break interrupt to occur:
• A CPU-generated address (the address in the program counter)
matches the contents of the break address registers.
• Software writes a ‘1’ to the BRKA bit in the break status and
control register (BRKSCR).
When a CPU-generated address matches the contents of the break
address registers, the break interrupt begins after the CPU completes its
current instruction. A return from interrupt instruction (RTI) in the break
routine ends the break interrupt and returns the MCU to normal
operation. Figure 11 shows the structure of the break module.
MC68HC08AZ32
124
Break Module
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2-brk
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