MC68HC08AZ32 Datasheet, PDF (175/424 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Serial Communications Interface Module (SCI)
Functional description
Table 3. SCI receiver I/O register summary
Register name
Bit 7 6
5
4
3
2
1 Bit 0 Addr.
SCI control register 1 (SCC1)LOOPS ENSCI TXINV M WAKE ILTY PEN PTY $0013
SCI control register 2 (SCC2) SCTIE TCIE SCRIE ILIE TE RE RWU SBK $0014
SCI control register 3 (SCC3) R8 T8
R
R ORIE NEIE FEIE PEIE $0015
SCI status register 1 (SCS1) SCTE TC SCRF IDLE OR NF FE PE $0016
SCI status register 2 (SCS2)
BKF RPF $0017
SCI data register (SCDR)
$0018
SCI baud rate register (SCBR)
SCP1 SCP0
SCR2 SCR1 SCR0 $0019
= Unimplemented
R = Reserved
Character length
The receiver can accommodate either 8-bit or 9-bit data. The state of
the M bit in SCI control register 1 (SCC1) determines character
length. When receiving 9-bit data, bit R8 in SCI control register 2
(SCC2) is the ninth bit (bit 8). When receiving 8-bit data, bit R8 is a
copy of the eighth bit (bit 7).
Character reception
During an SCI reception, the receive shift register shifts characters in
from the PTE1/RxD pin. The SCI data register (SCDR) is the
read-only buffer between the internal data bus and the receive shift
register.
After a complete character shifts into the receive shift register, the
data portion of the character transfers to the SCDR. The SCI receiver
full bit, SCRF, in SCI status register 1 (SCS1) becomes set, indicating
that the received byte can be read. If the SCI receive interrupt enable
bit, SCRIE, in SCC2 is also set, the SCRF bit generates a receiver
CPU interrupt request.
11-sci
MOTOROLA
Serial Communications Interface Module (SCI)
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MC68HC08AZ32
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