MC68HC08AZ32 Datasheet, PDF (123/424 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
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Functional description
SSREC — Short stop recovery bit
SSREC enables the CPU to exit stop mode with a delay of 32
CGMXCLK cycles instead of a 4096 CGMXCLK cycle delay.
1 = STOP mode recovery after 32 CGMXCLK cycles
0 = STOP mode recovery after 4096 CGMXCLK cycles
If using an external crystal oscillator, the SSREC bit should not be set.
COPRS — COP rate select
COPRS is similar to COPL (please note that the logic is reversed) as
it determines the timeout period for the COP.
1 = COP timeout period is 2¹⁸ — 2⁴ CGMXCLK cycles.
0 = COP timeout period is 2¹³ — 2⁴ CGMXCLK cycles.
STOP — STOP enable bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP disable bit
COPD disables the COP module. See
Computer Operating Properly Module (COP) on page 143.
1 = COP module disabled
0 = COP module enabled
3-maskops
MOTOROLA
Mask Options
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MC68HC08AZ32
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