MC68HC08AZ32 Datasheet, PDF (176/424 Pages) Motorola, Inc – Advance Information

Freescale Semiconductor, Inc.
Serial Communications Interface Module (SCI)
Data sampling
The receiver samples the PTE1/RxD pin at the RT clock rate. The RT
clock is an internal signal with a frequency 16 times the baud rate. To
adjust for baud rate mismatch, the RT clock is resynchronized at the
following times (see Figure 4):
• After every start bit
• After the receiver detects a data bit change from ‘1’ to ‘0’ (after the
majority of data bit samples at RT8, RT9, and RT10 returns a valid
‘1’ and the majority of the next RT8, RT9, and RT10 samples
returns a valid ‘0’).
PTE1/RxD
SAMPLES
RT
CLOCK
RT CLOCK
STATE
RT CLOCK
RESET
START BIT
LSB
START BIT
QUALIFICATION
START BIT
DATA
VERIFICATION SAMPLING
Figure 4. Receiver data sampling
To locate the start bit, data recovery logic does an asynchronous
search for a ‘0’ preceded by three ‘1’s. When the falling edge of a
possible start bit occurs, the RT clock begins to count to 16.
MC68HC08AZ32
174
Serial Communications Interface Module (SCI)
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