MC92501 Datasheet, PDF (28/52 Pages) Motorola, Inc – ATM Cell Processor

11.4.2. Egress Processing Configuration Register (EPCR)
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0 EGCTE ECCR ERCR ESFCE ESFNE ESPE ESBCE ESBNE
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EPCC
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EIP
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EBCC
EPCV RGFC 0
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EGCTEÑGlobal Egress CLP Transparency Enable
This bit enables CLP transparency function on the egress. See Section 6 for details.
ECCRÑEgress Check CRC on RM Cells
This bit determines whether the CRC of RM cells that are received in the egress is checked.
0 = The CRC of RM cells that are recevied in the egress is not checked.
1 = The CRC of RM cells that are received in the egress is checked and if it is not okay, then the cell is removed and can be
copied to the microprocessor.
ERCRÑEgress Recalculate CRC on RM Cells
This bit determines whether the CRC of egress RM cells is recalculated.
0 = The CRC of egress RM cells is not recalculated.
1 = The CRC of egress RM cells is recalculated.
ESFCEÑGlobal Egress Set FRM CI Enable
This bit enables setting CI bit in forward RM cells received in egress. See Section 5.4.2.
0 = Setting CI bit in forward RM cells received in egress is disabled.
1 = Setting CI bit in forward RM cells received in egress is enabled.
ESFNEÑGlobal Egress Set FRM NI Enable
This bit enables setting NI bit in forward RM cells received in egress. See Section 5.4.2.
0 = Setting NI bit in forward RM cells received in egress is disabled.
1 = Setting NI bit in forward RM cells received in egress is enabled.
ESPEÑGlobal Egress Set PTI Enable
This bit enables setting PTI[1] bit in cells with PTI[2] = 0 which are received in egress. See Section 5.4.2.
0 = Setting PTI[1] bit in cells with PTI[2] = 0 which are received in egress is disabled.
1 = Setting PTI[1] bit in cells with PTI[2] = 0 which are received in egress is enabled.
ESBCEÑGlobal Egress Set BRM CI Enable
This bit enables setting CI bit in backward RM cells received in egress. See Section 5.4.2.
0 = Setting CI bit in backward RM cells received in egress is disabled.
1 = Setting CI bit in backward RM cells received in egress is enabled.
ESBNEÑGlobal Egress Set BRM NI Enable
This bit enables setting NI bit in backward RM cells received in egress. See Section 5.4.2.
0 = Setting NI bit in backward RM cells received in egress is disabled.
1 = Setting NI bit in backward RM cells received in egress is enabled.
EPCCÑEgress Policing Counters Control
This Þeld determines which counters appear in the Policing Counters Table if egress UPC is enabled. (The UPCFÑUPC Flow
bit in the ACR is set.) It also determines the size of each record in the table.
000 = The policing table does not exist.
001 = The policing table contains three counters and one reserved long word: DSCD0, DSCD1, TAG, Reserved.
010 = The policing table contains three counters: DSCD0, DSCD1, TAG.
011 = The policing table contains two counters: DSCD, TAG.
100 = The policing table contains one counter: TAG.
101 = The policing table contains one counter: DSCD.
110 = Reserved
111 = Reserved
MC92501
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MOTOROLA