MC92501 Datasheet, PDF(1/52 Page) Motorola, Inc

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MC92501 Datasheet, PDF (1/52 Pages) Motorola, Inc – ATM Cell Processor

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Advance Information

ATM Cell Processor

The ATM Cell Processor (MC92501) is an Asynchronous Transfer Mode (ATM)

layer device composed of dedicated high-performance ingress and egress cell

processors combined with UTOPIA Level 2-compliant physical (PHY) and switch

interface ports (see Block Diagram). The MC92501 is a second generation ATM

cell processor in MotorolaÃs 92500 series. This document provides information

on the new features offered by the second generation ATM cell processor. This

document, combined with MC92500/D, provides the complete speciÃcation for

the ATM cell processor.

New Features of the MC92501:

Â¥ Implements ATM Layer Functions for Broadband ISDN According to ATM

Forum UNI 4.0 and TM 4.0 SpeciÃcations, ITU Recommendations, and

Bellcore Recommendations

Â¥ Provides ABR Relative Rate Marking and EFCI Marking According to TM 4.0

Â¥ Selective Discard CLP = 1 (or CLP = 0+1) Flow on Selected Connections

Â¥ UTOPIA Level 2 PHY Interface and UTOPIA ATM Layer Interface

Â¥ Supports Both Partial Packet Discard (PPD) and Early Packet Discard (EPD)

Â¥ Change ABR RM Cell Priority

Â¥ Support for CLP Transparency

Existing MC92500 Features:

Â¥ Full-Duplex Operation at Data Rates up to 155 Mbit/sec

Â¥ Performs Internal VPI and VCI Address Compression for up to 64K VCs

Â¥ CLP-Aware Peak, Average, and Burst-Length Policing with Programmable

Tag/Drop Action Per Policer

Â¥ Supports up to 16 Physical Links Using Dedicated Ingress/Egress MultiPHY

Control Signals

Â¥ Each Physical Link Can Be ConÃgured as Either a UNI or NNI Port

Â¥ Supports Multicast, Multiport Address Translation

Â¥ Maintains Both Virtual Connection and Physical Link Counters on Both

Ingress and Egress Cell Flows

Â¥ Provides a Flexible 32-Bit External Memory Port for Context Management

Â¥ Automated AIS, RDI, CC, and Loopback Functions with Performance

Monitoring Block Test on All 64K Connections

Â¥ Programmable 32-Bit Microprocessor Interface Supporting Big-Endian or

Little-Endian Bus Formats

Â¥ Bidirectional UPC or NPC Design with up to Four Leaky Buckets Per

Connection

Â¥ Supports a Programmable Number of Additional Switch Overhead

Parameters Allowing Adaptation to Any Switch Routing Header Format

Â¥ Provides Per-Link Cell Counters in Both Directions

Order this document

by MC92501/D

MC92501

GC SUFFIX

GTBGA

CASE 1208

ORDERING INFORMATION

MC92501GC GTBGA

This document contains information on a new product. SpeciÃcations and information herein are subject to change without notice.

REV 1.2

2/98

TN98020500

MC92501

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