MC92501 Datasheet, PDF (25/52 Pages) Motorola, Inc – ATM Cell Processor

11.2.3. ATMC CFB Revision Register (ARR)
The AMRV Þeld has been updated.
Table 4. Values of ATMC CFB Revision Fields
AMRV
000001
ASRV
000000
ATMC CFB Revision
MC92501 (MC92500 Revision B)
11.2.4. MC92501 Revision Register (RR)
The MRV Þeld has been updated.
Table 5. Values of the MC92501 Revision Fields
ID
10000000000000000000
MRV
000001
SRV
000000
MC92501 Revision
MC92501 (MC92500 Revision B)
11.3. Control Registers
The following registers have been added.
11.3.1. Ingress Processing Control Register (IPLR)
This register has the following structure:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ICNG IAME
ICNGÑGlobal Ingress Congestion NotiÞcation
This bit notiÞes the MC92501 whether there is congestion in the ingress ßow. See Section 4.
0 = No ingress congestion.
1 = Ingress congestion. The MC92501 performs selective discard according to per-connection CIMEÑConnection Ingress
Marking Enable bit.
IAMEÑGlobal Ingress ABR Mark Enable
This bit, when set, indicates that current ingress ßow status implies that the MC92501 should perform RR marking and/or EFCI
marking if enabled. See Section 5.4.1.
11.3.2. Egress Processing Control Register (EPLR)
This register has the following structure:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 EAME
EAMEÑGlobal Egress ABR Mark Enable
This bit, when set, indicates that current egress ßow status implies that the MC92501 should perform RR marking and/or EFCI
marking if enabled. See Section 5.4.2.
MOTOROLA
MC92501
25