MC92501 Datasheet, PDF (23/52 Pages) Motorola, Inc – ATM Cell Processor

SECTION 10. UTOPIA LEVEL 2 PHY INTERFACE
The MC92501 PHY interface can be programmed to
support UTOPIA Level 2. It allows for operation of one TxClav
and one RxClav signal.
On the ingress direction, the MC92501 supports address
polling on up to 16 physical links. It scans all the links in a
round robin fashion and decides from which PHY to read the
next cell.
UTOPIA Level 2 is enabled on ingress by programming the
IUMÑIngress UTOPIA Mode bit of the Ingress PHY
ConÞguration Register (IPHCR). In this mode, Receive PHY
ID 0-3/Receive Address 0-3 (RXPHYID0-RXPHYID3/
RXADD0-RXADDR3) signals function as RXADDR0-
RXADDR4.
NOTE
RXADDR4 is a new functional signal in MC92501
that was a NC (No Connect) on the MC92500.
UTOPIA Level 2 is enabled on egress by programming the
EUMÑEgress UTOPIA Mode bit of the Egress PHY
ConÞguration Register (EPHCR). In this mode, the Transmit
PHY ID 0-3 /Transmit Address 0-3 (TXPHYID0-TXPHYID3/
TXADDR0-TXADDR3) signals and the Transmit Next PHY ID
Valid/Transmit Address 4 (TXPHYIDV/TXADDR4) signal are
used as TXADDR0-TXADDR4. The MC92501 polls the link of
the cell in its egress PHY IF FIFO, and when enabled it outputs
the cell to the link PHY. The MC92501 performs address
polling on all other links as well in order to enable external
logic to monitor the PHYÕs status.
Figure 17 illustrates an application on which external logic
monitors the RxClav signal while the MC92501 is polling the
PHY devices. Based on this information, the external logic can
input cells to the MC92501 egress ßow.
PHY Device
PHY Device
PHY Device
PHY Device
TxAddr
MC92501
Feedback
TxAddr
TxClav
External Logic
Figure 17. Feedback Using TxClav
MOTOROLA
MC92501
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