MC92501 Datasheet, PDF (20/52 Pages) Motorola, Inc – ATM Cell Processor

SECTION 7. INDIRECT EXTERNAL MEMORY ACCESS
7.1. Overview
The MC92500 allows the processor to access its external
memory for the duration of one cell processing time out of N,
where N is programmable. The MC92501 will additionally
allow the processor to access external memory while
operating on the cell stream. The indirect access takes place
at least once in every cell processing slot. The indirect access
is not performed during maintenance.
7.2. User Interface
Indirect external memory access is performed using two
registers: the Indirect External Memory Access Address
Register (IAAR) and the Indirect External Memory Access
Data Register (IADR).
7.2.1. Write Access
In order to write to the external memory, the processor
should poll the IABÑIndirect External Memory Access Busy
bit in the IAAR register to verify the status of the IAAR and
IADR registers. If IAB is clear, then the processor can write
the address data and status into the appropriate registers.The
IADÑIndirect External Memory Address DIR bit is is set to 0
for a write operation. Writing to the IAAR register triggers the
MC92501 to wait for a dedicated clock to write the data into
the external memory using the given address and data. Once
the MC92501 Þnishes writing, it clears the IABÑIndirect
External Memory Access Busy bit in the IAAR register.
7.2.2. Read Access
In order to read from the external memory, the processor
should poll the IABÑIndirect External Memory Access Busy
bit in the IAAR register to verify that it may write the IAAR
register. If IAB is clear, then the processor can write the
address, size, and direction into the appropriate registers. For
a read operation, the IADÑIndirect External Memory Address
DIR bit is set to 1. Writing to the IAAR register triggers the
MC92501 to wait for a dedicated clock, and read the data from
external memory using the given address and write the data
into the IADR register. Once the data was written into the IADR
register, the MC92501 clears the IABÑIndirect External
Memory Access Busy bit in the IAAR register. The processor
then may read the data from the IADR register.
The address space which is covered by this interface
includes all the non-destructive external memory access and
an external address compression device.
NOTE
Indirect write access to an external memory
space, which can be written by the MC92501, is
not recommended. For example, an indirect write
access to a ßag-table record of an active
connection is not recommended. It is advisable to
use the maintenance cell slot for this purpose.
Table 1 summarizes indirect access Þelds:
Table 1. Indirect Access Fields
IADÑ
Indirect
External
Memory
Access DIR
0
0
0
0
0
1
IAWÑ
Indirect
External
Memory
Access Size
0
1
1
1
1
x
Least
SigniÞcant
Bit of IAAÑ
Indirect
External
Memory
Access
Address
x
0
0
1
1
x
DOÑData
Order
x
0
1
0
1
x
Function
Write IADR[31:00] to external memory word bits [31:00]
Write IADR[31:16] to external memory word [31:16]
Write IADR[15:00] to external memory word [15:00]
Write IADR[15:00] to external memory word [15:00]
Write IADR[31:16] to external memory word [31:16]
Read external memory word bits [31:00] to IADR[31:00]
MC92501
20
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