MC92501 Datasheet, PDF (14/52 Pages) Motorola, Inc – ATM Cell Processor

Global Reg.
CellÕs Overhead
Context Bit
Ingress
Status
Collection
Ingress Flow Status
Ingress
Action:
Marking
Set CI
Set NI
Set PTI
Global Reg.
CellÕs Overhead
Context Bit
Global Registers
Egress
Status
Collection
Egress Flow Status
Global Registers
Context Bits
Cell Type
Egress
Action:
Marking
Set CI
Set NI
Set PTI
Figure 11. Cell Marking Scheme
There are various ways to inform the MC92501 that it should
mark a cell due to the ingress ßow status or the egress ßow
status. This scheme also shows that the status of the ingress
ßow, the status of the egress ßow, global registers, a context
bit, and the cell type impact the decision of setting CI, NI, and
PTI. Following is a detailed description of each of the function
boxes.
5.4.1. Sources for Ingress Flow Status
The ingress ßow status is gathered from three sources:
global register, cellÕs overhead, or context bit.
5.4.1.1. Ingress Flow Status from Global Register
The switch fabric can notify the MC92501 that it should mark
cells because of the ingress ßow status by setting the IAMEÑ
Global Ingress ABR Mark Enable bit in the Ingress Processing
Control Register (IPLR).
5.4.1.2. Ingress Flow Status from CellÕs Overhead
The switch fabric can notify the MC92501 that it should mark
cells because of the ingress ßow status of connection #n by
setting the IFSÑOverhead Ingress Flow Status bit in the
overhead of egress cells belonging to that connection. The
location of this bit in the overhead is programmable using the
EIBYÑIFS Byte Location bit and the EIBIÑIFS Bit Location
bit in the Egress Switch Overhead Information Register 1
(ESOIR1). This bit is enabled by the EIASÑGlobal IFS Enable
bit in the Egress Switch Interface ConÞguration Register
(ESWCR). The MC92501 can be programmed that in such a
case it will mark egress BRM cells.
5.4.1.3. Ingress Flow Status from Context Memory
The switch fabric can notify the MC92501 that it should mark
cells because of the ingress ßow status of connection #n by
setting the IFSÑOverhead Ingress Flow Status bit in the
overhead of egress cells belonging to that connection. (See
Section 5.4.1.2 for details on enabling of IFSÑOverhead
Ingress Flow Status bit and its location.) When the MC92501
receives that cell, it copies the bit into the CIFSÑConnection
Ingress Flow Status bit in the Common Parameters Extension
Word of connection #n. The MC92501 can be programmed
that in such a case it will mark ingress FRM cells or perform
EFCI marking.
5.4.1.4. Logic of Ingress Flow Status
The ingress ßow status equals 1 if:
IAME = 1 OR
IFS = 1 and EIAS = 1 and egress = 1 OR
CIFS = 1 and EIAS = 1 and ingress = 1
Where:
IAME = Global Ingress ABR Mark Enable
IFS = Overhead Ingress Flow Status
EIAS = Global IFS Enable
CIFS = Connection IFS Enable
Egress = Programmed Overhead Egress Bit
Ingress = Programmed Overhead Ingress Bit
5.4.2. Sources for Egress Flow Status
The egress ßow status is gathered from three sources:
global register, cellÕs overhead, and context memory.
5.4.2.1. Egress Flow Status from Global Register
The switch fabric can notify the MC92501 that it should mark
cells because of the egress ßow status by setting the EAMEÑ
Global Egress ABR Mark Enable bit in the Egress Processing
Control Register (EPLR).
5.4.2.2. Egress Flow Status from CellÕs Overhead
The switch fabric can notify the MC92501 that it should mark
cells because of the egress ßow status of connection #n by
setting the EFSÑOverhead Egress Flow Status bit in the
overhead of egress cells belonging to that connection. The
MC92501
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