MC92501 Datasheet, PDF (15/52 Pages) Motorola, Inc – ATM Cell Processor

location of this bit in the overhead is programmable using the
EEBYÑEFS Byte Location bit and the EEBIÑEFS Bit
Location bit in the Egress Switch Overhead Information
Register 1 (ESOIR1). This bit is enabled by the EEASÑGlobal
EFS Enable bit in the Egress Switch Interface ConÞguration
Register (ESWCR). The MC92501 can be programmed that
in such a case it will mark egress FRM cells or perform EFCI
marking.
5.4.2.3. Egress Flow Status from Context Memory
The switch fabric can notify the MC92501 that it should mark
cells because of the egress ßow status of connection #n by
setting the EFSÑOverhead Egress Flow Status bit in the
overhead of egress cells belonging to that connection. (See
Section 5.4.2.2 for details on enabling of EFSÑOverhead
Egress Flow Status bit and its location.) When the MC92501
receives that cell, it copies the bit into the CEFSÑConnection
Egress Flow Status bit in the Common Parameters Extension
Word of connection #n. The MC92501 can be programmed
that in such a case it will mark ingress BRM cells.
5.4.2.4. Logic of Egress Flow Status
The egress ßow status equals 1 if:
EAME = 1 OR
EFS = 1 and EEAS = 1 and egress = 1 OR
CEFS = 1 and EEAS = 1 and ingress = 1
Where:
EAME = Global Egress ABR Mark Enable
EFS = Overhead Egress Flow Status
EEAS = Global EFS Enable
CEFS = Connection EFS Enable
Egress = Programmed Overhead Egress Bit
Ingress = Programmed Overhead Ingress Bit
5.4.3. Ingress ABR Marking Bits
The MC92501 can mark cells as a result of either ingress
ßow status or egress ßow status.
In the case where ingress ßow status is asserted, the
MC92501 can perform one or more of the following:
¥ Set CI bit in an ingress FRM cell Ñ when the ISFCEÑ
Global Ingress Set FRM CI Enable bit in the Ingress
Processing ConÞguration Register (IPCR) is set.
¥ Set NI bit in an ingress FRM cell Ñ when the ISFNEÑ
Global Ingress Set FRM NI Enable bit in the IPCR is set.
¥ Set PTI[1] bit in an ingress cell whose PTI[2] = 0 Ñ when
the ISPEÑGlobal Ingress Set PTI Enable bit in the IPCR
is set.
In the case where egress ßow status is asserted, the
MC92501 can perform one or more the following:
¥ Set CI bit in an ingress BRM cell Ñ when the ISBCEÑ
Global Ingress Set BRM CI Enable bit in the IPCR is set.
¥ Set NI bit in an ingress BRM cell Ñ when the ISBNEÑ
Global Ingress Set BRM NI Enable bit in the IPCR is set.
All cell marking on the ingress is enabled on a per-
connection basis by the CIMEÑConnection Ingress Marking
Enable bit in the Common Parameters Extension Word.
5.4.3.1. Logic of Ingress ABR Marking Bits
The CI bit is set if:
FRM cell and CIME = 1 and ingress ßow status = 1
and ISFCE = 1 OR
BRM cell and CIME = 1 and egress ßow status = 1
and ISBCE = 1
The NI bit is set if:
FRM cell and CIME = 1 and ingress ßow status = 1 and
ISFNE = 1 OR
BRM cell and CIME = = 1 and egress ßow status = 1 and
ISBNE = 1
The PTI[1] bit is set if:
PTI[2] = 0 and CIME = 1 and ingress ßow status = 1 and
ISPE = 1
Where:
CIME = Connections Ingress Marking Enable
FRM Cell = Cell marked as FRM cell
BRM Cell = Cell marked as BRM cell
Ingress Flow Status = Set as deÞned in Section 5.4.1.4
Egress Flow Status = Set as deÞned in Section 5.4.2.4
ISFCE = Global Ingress Set FRM CI Enable
ISFNE = Global Ingress Set FRM NI Enable
ISPE = Global Ingress Set PTI Enable
ISBCE = Global Ingress Set BRM CI Enable
ISBNE = Global Ingress Set BRM NI Enable
5.4.4. Egress ABR Marking Bits
The MC92501 can mark cells as a result of either ingress
ßow status or egress ßow status.
In the case where egress ßow status is asserted, the
MC92501 can perform one or more of the following:
¥ Set CI bit in an egress FRM cell Ñ when the ESFCEÑ
Global Egress Set FRM CI Enable bit in the Egress
Processing ConÞguration Register (EPCR) is set.
¥ Set NI bit in an egress FRM cell Ñ when the ESFNEÑ
Global Egress Set FRM NI Enable bit in the EPCR is set.
¥ Set PTI[1] bit in an egress cell whose PTI[2] = 0 Ñ when
the ESPEÑGlobal Egress Set PTI Enable bit in the EPCR
is set.
In the case where ingress ßow status is asserted, the
MC92501 can perform one or more the following:
¥ Set CI bit in an egress BRM cell Ñ when the ESBCEÑ
Global Egress Set BRM CI Enable bit in the EPCR is set.
¥ Set NI bit in an egress BRM cell Ñ when the ESBNEÑ
Global Egress Set BRM NI Enable bit in the EPCR is set.
All cell marking on the egress is enabled on a per-
connection basis by the CEMEÑConnection Egress Marking
Enable bit in the Common Parameters Extension Word.
MOTOROLA
MC92501
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