MC92501 Datasheet, PDF (27/52 Pages) Motorola, Inc – ATM Cell Processor

11.4. Configuration Register
The following registers have been updated. The Þelds that have been added are in bold.
11.4.1. Ingress Processing Configuration Register (IPCR)
31
30
29
0
0
0
15
14
13
IPCC
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0 IGCTE ICCR IRCR ISFCE ISFNE ISPE ISBCE ISBNE
12
11
10
9
8
7
6
5
4
3
2
1
0
0
IGZC IUHC
IIP IROE
0
IBCC
IPCV
IAPE
IACE
IGCTEÑGlobal Ingress CLP Transparency Enable
This bit enables CLP transparency function on the ingress. See Section 6 for details.
ICCRÑIngress Check CRC on RM Cells
This bit determines whether the CRC of RM cells that are received in the ingress is checked.
0 = The CRC of RM cells that are recevied in the ingress is not checked.
1 = The CRC of RM cells that are received in the ingress is checked and if it is not okay, then the cell is removed and can be
copied to the microprocessor.
IRCRÑIngress Recalculate CRC on RM Cells
This bit determines whether the CRC of ingress RM cells is recalculated.
0 = The CRC of ingress RM cells is not recalculated.
1 = The CRC of ingress RM cells is recalculated.
ISFCEÑGlobal Ingress Set FRM CI Enable
This bit enables setting CI bit in forward RM cells received in ingress. See Section 5.4.3 for details.
0 = Setting CI bit in forward RM cells received in ingress is disabled.
1 = Setting CI bit in forward RM cells received in ingress is enabled.
ISFNEÑGlobal Ingress Set FRM NI Enable
This bit enables setting NI bit in forward RM cells received in ingress. See Section 5.4.3 for details.
0 = Setting NI bit in forward RM cells received in ingress is disabled.
1 = Setting NI bit in forward RM cells received in ingress is enabled.
ISPEÑGlobal Ingress Set PTI Enable
This bit enables setting PTI[1] bit in cells with PTI[2] = 0 which are received in ingress. See Section 5.4.3 for details.
0 = Setting PTI[1] bit in cells with PTI[2] = 0 which are received in ingress is disabled.
1 = Setting PTI[1] bit in cells with PTI[2] = 0 which are received in ingress is enabled.
ISBCEÑGlobal Ingress Set BRM CI Enable
This bit enables setting CI bit in backward RM cells received in ingress. See Section 5.4.3 for details.
0 = Setting CI bit in backward RM cells received in ingress is disabled.
1 = Setting CI bit in backward RM cells received in ingress is enabled.
ISBNEÑGlobal Ingress Set BRM NI Enable
This bit enables setting NI bit in backward RM cells received in ingress. See Section 5.4.3 for details.
0 = Setting NI bit in backward RM cells received in ingress is disabled.
1 = Setting NI bit in backward RM cells received in ingress is enabled.
IROEÑIngress RM Overlay Enable
This bit enables updating switch parameter words in the case of RM cells. See Section 5.5 for details.
IPCVÑIngress Features Enable
This bit should be set when the following features are used: packet-based UPC, selective discard, and CLP transparency.
MOTOROLA
MC92501
27