M37754FFCGP Datasheet, PDF (65/68 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION

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ITSUBISHI MICROCOMPUTERS
M37754FFCGP
M37754FFCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
<NOTE> External bus timing when internal memory area is accessed (2-φ access) in high-speed
running
(VCC = 5 V±10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) ≤ 40 MHz when the clock source select bit = “0”^∗)
f (XIN) = 40 MHz^∗∗
Symbol
Parameter
Min.
Max.
Bus timing
data formula
Unit
tw(φH), tw(φL) φ high-level pulse width, φ low-level pulse width
5
1 × 10⁹
f(XIN)
– 20
ns
td(φ1–WR)
___
WR output delay time
–7
12
ns
td(φ1–RD)
tw(W^__R)
tw(R^_D^_)
___
RD output delay time
___
WR low-level pulse width
___
RD low-level pulse width
td(A–WR)
Address output delay time
td(A–RD)
Address output delay time
td(A–ALE)
td(BHE–WR)
td(BHE–RD)
td(BHE–ALE)
Address output delay time
____
BHE output delay time
____
BHE output delay time
____
BHE output delay time
td(CS–WR)
Chip select output delay time
td(CS–RD)
Chip select output delay time
td(CS–ALE)
Chip select output delay time
–7
12
ns
5
1 × 10⁹
f(XIN)
– 20
ns
5
1 × 10⁹
f(XIN)
– 20
ns
25
2 × 10⁹
f(XIN)
– 25
ns
25
2 × 10⁹
f(XIN)
– 25
ns
10
2 × 10⁹
f(XIN)
– 40
ns
25
2 × 10⁹
f(XIN)
– 25
ns
25
2 × 10⁹
f(XIN)
– 25
ns
10
2 × 10⁹
f(XIN)
– 40
ns
25
2 × 10⁹
f(XIN)
– 25
ns
25
2 × 10⁹
f(XIN)
– 25
ns
10
2 × 10⁹
f(XIN)
– 40
ns
td(WR–DLQ/DHQ) Data output delay time
tpxz(WR–DLZ/DHZ) Floating start delay time
35
————
ns
30
1 × 10⁹
f(XIN)
+5
ns
td(ALE–WR)
ALE output delay time
4
————
ns
td(ALE–RD)
ALE output delay time
tw(ALE)
ALE pulse width
th(WR–A)
Address hold time
th(RD–A)
td(WR–BHE)
td(RD–BHE)
Address hold time
____
BHE hold time
____
BHE hold time
td(WR–CS)
Chip select hold time
td(RD–CS)
Chip select hold time
th(WR–DLQ/DHQ) Data hold time
tpzx(WR–DLZ/DHZ) Floating release delay time
4
————
ns
10
1 × 10⁹
f(XIN)
– 15
ns
10
1 × 10⁹
f(XIN)
– 15
ns
10
1 × 10⁹
f(XIN)
– 15
ns
10
1 × 10⁹
f(XIN)
– 15
ns
10
1 × 10⁹
f(XIN)
– 15
ns
10
1 × 10⁹
f(XIN)
– 15
ns
10
1 × 10⁹
f(XIN)
– 15
ns
15
1 × 10⁹
f(XIN)
– 10
ns
0
————
ns
∗^{: f(XIN) ≤ 20 MHz when the clock source select bit = “1”.}
∗∗^{: f(XIN) = 20 MHz when the clock source select bit = “1”.}
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