M37754FFCGP Datasheet, PDF (48/68 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION

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MITSUBISHI MICROCOMPUTERS
M37754FFCGP
M37754FFCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
Switching characteristics (VCC = 5 V±10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz when the clock source select bit = “0”^∗,
unless otherwise noted)
Memory expansion and Microprocessor mode : Low-speed running
Symbol
tw(φH), tw(φL)
td(φ1–WR)
td(φ1–RD)
tw(W^__R)
tw(R^_D^_)
td(A–WR)
td(A–RD)
td(A–ALE)
td(BHE–WR)
td(BHE–RD)
td(BHE–ALE)
td(CS–WR)
td(CS–RD)
td(CS–ALE)
td(WR–DLQ/DHQ)
tpxz(WR–DLZ/DHZ)
td(ALE–WR)
td(ALE–RD)
tw(ALE)
th(WR–A)
th(RD–A)
th(WR–BHE)
th(RD–BHE)
th(WR–CS)
th(RD–CS)
th(WR–DLQ/DHQ)
tpzx(WR–DLZ/DHZ)
td(LA–WR)
td(LA–RD)
td(LA–ALE)
th(ALE–LA)
tpxz(RD–DLZ)
tpzx(RD–DLZ)
td(WR–PiQ)
Parameter
φ high-level pulse width, φ low-level pulse width (Note)
___
WR output delay time
__
RD output delay time
___
WR low-level pulse width (Note)
RD low-level pulse width (Note)
Address output delay time (Note)
Address output delay time (Note)
Address output delay time (Note)
____
BHE output delay time (Note)
____
BHE output delay time (Note)
____
BHE output delay time (Note)
Chip select output delay time (Note)
Chip select output delay time (Note)
Chip select output delay time (Note)
Data output delay time
Floating start delay time (Note)
ALE output delay time
ALE output delay time
ALE pulse width (Note)
Address hold time (Note)
Address hold time (Note)
BHE hold time (Note)
BHE hold time (Note)
Chip select hold time (Note)
Chip select hold time (Note)
Data hold time (Note)
Floating release delay time
Address output delay time (Note)
Address output delay time (Note)
Address output delay time (Note)
Address hold time
Floating start delay time
Floating release delay time (Note)
Port Pi data output delay time (i = 4—9, 11)
2-φ access 3-φ access 4-φ access
Min. Max. Min. Max. Min. Max. ^Unit
20
20
20
ns
–7 12 –7 12 –7 12 ns
–7 12 –7 12 –7 12 ns
60
140
140
ns
60
140
140
ns
15
15
95
ns
15
15
95
ns
8
8
55
ns
15
15
95
ns
15
15
95
ns
8
8
55
ns
15
15
95
ns
15
15
95
ns
8
8
55
ns
35
35
35 ns
30
30
30 ns
4
4
4
ns
4
4
4
ns
22
22
62
ns
10
10
10
ns
10
10
10
ns
10
10
10
ns
10
10
10
ns
10
10
10
ns
10
10
10
ns
15
15
15
ns
0
0
0
ns
12
12
92
ns
12
12
92
ns
5
5
52
ns
9
9
25 (Note)
ns
5
5
5
ns
18
18
18
ns
60
60
60 ns
∗^{: f(XIN) = 12.5 MHz when the clock source selet bit = “1”}
Note: Since the values depend on external clock input frequency f(XIN), calculate them using the bus timing data formula on the next page.
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